Sl.no:
|
Parameter/Feature
|
RISC
|
CISC
|
1
|
Abbreviation
|
Reduced Instruction Set Computer
|
Complex Instruction Set Computer
|
2
|
Clock Cycle Per Instruction (CPI)
|
1(except LOAD and STORE)
|
Multiple
|
3
|
Average Clock Cycle Per Instruction (CPI)
|
1.5
|
2 to 15
|
4
|
Instruction Format
|
Fixed(usually 32 bits)
|
Varies
|
5
|
Performance Optimization
|
Software-centric approach
|
Hardware-centric approach
|
6
|
Coding
|
More lines of Code
|
Simple
|
7
|
Code Expansion
|
Can be Problematic
|
Not a problem
|
8
|
Complexity
|
Lies in compiler
|
Lies in microprogram
|
9
|
Instruction Set
|
Has Primitive instructions
|
Has variety of different instructions
|
10
|
Complex Addressing Modes
|
Synthesized using the software
|
Already supports complex addressing modes
|
11
|
Register Sets
|
Multiple
|
Unique
|
12
|
Total Registers
|
More than 256
|
Typically 6 to 16
|
13
|
Register Operands Per Instructon
|
Upto 3
|
Upto 2
|
14
|
No Of Instructions
|
Less
|
More
|
15
|
Instructions Accesing Memory
|
Only LOAD and STORE
|
Almost all from same set
|
16
|
RAM Usage
|
Heavy use of RAM(can cause bottleneck if RAM is limited)
|
Comparatively more efficient
|
17
|
Hardware Design Focus
|
Hardwired control
|
Micro-programmed control
|
18
|
Pipelining
|
Very High
|
Rare
|
19
|
Instruction Decoding
|
Simple
|
Complex
|
20
|
Transistors Usage
|
For memory registers
|
For storing complex instructions
|
21
|
Computation Operands
|
Register and Immediate only
|
Memory operands allowed
|
22
|
Disk Space
|
Space is saved
|
Space is wasted
|
23
|
Stalling
|
Mostly reduced in processors
|
Processors often stall
|
24
|
Portability
|
Less portable for design errors
|
Significant portable for design errors
|
25
|
Calculation Speed
|
Fast
|
Slow
|
26
|
Design Time
|
Less
|
Long
|
27
|
Memory Unit
|
Absent(uses a separate hardware to implement instructions)
|
Present
|
28
|
External Memory For Calculation Purpose
|
Not required
|
Needed
|
29
|
General Purpose Registers
|
32 to 192 with split data cache for instruction cache
|
8 to 24 general purpose registers with a unified cache for instructions and data (recent designs use split caches)
|
30
|
Memory Size Of Program
|
More space
|
Less space
|
31
|
Interruption
|
Responds to interrupt only at the proper place in instruction execution
|
Responds to an interrupt only at the end of execution
|
32
|
Conditional Jump
|
Based on a bit anywhere in memory
|
Based on status register bit
|
33
|
Instruction Format
|
Field Placement Varies
|
Regular Consistent placement of fields
|
34
|
|
Register to register: "LOAD" and "STORE" incorporated in instructions
|
Memory-to-memory: "LOAD" and "STORE" are independent instructions
|
35
|
Eg:
A = A * B; <<======this is C statement
|
LOAD R1, A <<<======this is assembly statement
LOAD R2, B <<<======this is assembly statement
PROD A, B <<<======this is assembly statement
STORE R3, A <<<======this is assembly statement
|
MULT A,B <<<======this is assembly statement
|
36
|
Processors
|
Ideal for processors performing dedicated operations
|
Ideal for processors performing a variety of operations
|
37
|
Instruction Fetching Time
|
Mostly same time
|
Different
|
38
|
Operands Per Instruction
|
Fixed
|
Variable
|
39
|
Applications
|
High-end applications such as video processing, telecommunications and image processing
|
Low-end applications such as security systems, home automation, etc.
|
40
|
Example
|
Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power Architecture, and SPARC
|
System/360, VAX, PDP-11, Motorola 68000 family, AMD and Intel x86 CPUs
|