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A $32$-$bit$ wide main memory unit with a capacity of $1\;GB$ is built using $256$ $M \times 4-bit$ DRAM chips. The number of rows of memory cells in the DRAM chip is $2^{14}$. The time taken to perform one refresh operation is $50$ $nanoseconds$. The refresh period is $2$ milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is_____.

edited | 7.4k views
+10

At start it seems simple RAM concept extended but after that it went out of track for me :p

Can't even guess the answer as it is NAT Question
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https://gatecse.in/gate-cse-2016-syllabus/
here it was clearly mentioned that questions on RAM wouldn't be there !!!

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To prevent this, external circuitry periodically reads each cell and rewrites it, restoring the charge on the capacitor to its original level.

Read/Write is happening as a part of refresh operation then why is it asked for separately ?

One more doubt why all the rows can not be refreshed in one cycle ?

@VS, @Subarna Das, @Ashwin Kulkarni, @ habedo007 and @Digvijay Pandey ji. What is your opinion ?

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Refreshing does not employ the normal memory operations (read and write cycles) used to access data, but specialized cycles called refresh cycles which are generated by separate counter circuits in the memory circuitry and interspersed between normal memory accesses

https://en.wikipedia.org/wiki/Memory_refresh#How_DRAM_refresh_works

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Chhotu During this refreshing the old(or already stored) data is read and rewritten into the cells but in ordinary read/write operation, data is read not for the purpose of restoring and "write" is to store new data into the cells.

If i am wrong then correct me.

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Why do they give information about the DRAM size and which chips are used for it in such questions?
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DRAM Starts from 21 minutes onwards

hope this could help !!!

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32 bit wide means page size is of 32 bits in the main memory.
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Refreshing of DRAM is this topic included in GATE2020 syllabus?
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Yes, it is there in CO.

One refresh operation takes $50ns$.
Total number of rows $= 2^{14}$

Total time to refresh all Rows $= 2^{14}\times 50\; ns = 819200 \;ns = 0.819200\;ms$
The Refresh Period is $2ms.$

$\%$ Time spent in refresh  $= \frac{Total\ time\ to\ Refresh\ all\ Rows}{Refresh\ period}*100$
$= \frac{0.8192ms}{2.0ms}*100$ $= 40.96\%$

$\%$ Time spent in Read/Write $= 100 - 40.96 = 59.04\%$

$= 59\%$ (Rounded to the closest Integer)

edited
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Great explanation :)
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All the chips are refreshed simultaneously?
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@Peach yes. Take a look at this question for better understanding:
https://gateoverflow.in/2178/gate2010-7

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It is said that "refresh period is 2 millisecond" ie the rows get refreshed every 2 seconds, why is the time take for refresh included in the period. Please correct my interpretation about period.
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In 2msec, the time given to refresh is 2^14*50 nsec and rest will be for read and write.We are just talking about time spent on read/write in 2msec only.
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Sir,

It is given that Refresh period is 2 ms ..so after every 2 ms all the rows should get refreshed .

Hence ..time to refresh one row  = 2ms / # of rows ..

But here given Refresh time for row is 50nsec...

Why so...which statergy of refresh is implied here..burst or distributed ??

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Bro refresh period is 2ms. It is upper limit, it means if we refresh a row now, it should be refreshed before that 2ms otherwise it would be faded. but we are refreshing all the rows in less than that time as given refresh time for a row is 50ns. So in the time remaining we could read or write.
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There would be 8 chips required in total.

All of them can be refreshed in parallel and in a single row of a DRAM chip, all cells can be refreshed in parallel.

So, total refresh time should be $2^{14} \times 50\,ns$
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Yes ...there is a single row of 8 dram chips.... :)
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but how to check its parallel and not serial architecture? As for total number of rows we need no.of rows per dram * no.of dram

so how to understand? Or always take Parallel?

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@habedo007
There we considered paralleled as per options what about NAT type as in here? How to decide?

On a 32bit machine, the maximum amount of memory is around 4GB and it's ok to have a capacity of less than 4GB. Because it depends on OS as well and might be less due to parts of address space being reserved, So the usable capacity of the main memory is 1GB, and this main memory may have been designed using more than 1 DRAM chips,
One DRAM chip size is 256M x 4bits=2^28 x 2^2 =2^30bits.
No. of DRAM chips needed to design main memory of size 1GB= 2^30*8 / 2^30=8. so 8 DRAM chips are needed. Now there are 2^14 rows in each DRAM chips. then how many cells(column) are there in one row or in one DRAM chip=2^30bits(Size of one DRAM) / 2^14=2^16.
The time taken to perform one refresh operation is for only 1 row of 1 DRAM chip and it is 50nsec. The refresh period is 2 msec means after every 2msec the DRAM chips need to be refreshed otherwise data stored in it will get lost. Now they are asking what is the percentage of time for meaningful operations(R/W) other than refresh overhead. so if we calculate refresh overhead itself, we can also derive percentage of time for meaningful operations(100%- refresh overhead%).
Given, the total number of rows is 2^14 and time taken to perform one refresh operation is 50 nanoseconds. So, total time taken to perform refresh operation on 1DRAM chip = 2^14*50 nanoseconds = 819200 nanoseconds = 0.819200 milliseconds. But the refresh period is 2 milliseconds.

Note:- All DRAM chips are refreshed simultaneously.

So, time spent in refresh period in percentage or REFRESH OVERHEAD= TIME TAKEN FOR 1 REFRESH OPERATION TO 1 DRAM CHIP / REFRESH INTERVAL

= (0.819200 milliseconds) / (2 milliseconds) = 0.4096 = 40.96% Hence, time spent in read/write operation = 100% - 40.96% = 59.04% = 59 (in percentage and rounded to the closet integer). So, answer is 59. edited
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@Nitesh Singh 2

Can u tell me one thing of question

See

A 32-bit wide main memory unit with a capacity of 1GB is built using

means already main memory has given main memory of size $2^{32}$ given, then why again given capacity 1GB.

But why there are two time declaration?

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@srestha Yeah! I feel the same. Can you tell why is there a discrepancy in the size of main memory? I am unable to find any resource that tells the difference.

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@srestha mam Is this explanation correct?

on a 32bit machine, the maximum amount of memory is around 4GB. and the usable capacity is 1GB. Because it depends on OS as well and might be less due to parts of address space being reserved.

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@Nitesh Singh 2

If we consider this line

Memory refresh is the process of periodically reading information from an area of computer memory and immediately rewriting the read information to the same area without modification, for the purpose of preserving the information.

Then , can we not say refresh operation only work on memory read or write. So, first line of this question, i.e.

A 32-bit wide main memory unit with a capacity of 1GB is built using 256 M×4−bit DRAM chips.

This line is just on memory capacity. So, this is not required part of this question??

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@Nitesh Singh 2 Can you explain .
No. of DRAM chips needed to design main memory of size 1GB= 2^30*8 / 2^30=8

2^30*8  ->  from where you calculating 8 ???

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It is given in GigaByteswe have to convert it into bits.

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ok ,got it. Thanks

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@Nitesh singh 2 can you explain what is the meaning of "refresh period"?
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@Nitesh Singh 2

I think the below statement you made is wrong.

On a 32bit machine, the maximum amount of memory is around 4GB

The maximum amount of memory actually depends on the address bus size. We always address words. We also call each word as a cell.

Word size = 32 bits in a 32-bit machine and data bus has 32 lines to carry 32 bits of data.

Word size = 64-bits in a 64-bit machine and data bus has 64 lines to carry 64 bits of data.

Ex: Say I have a 32-bit machine and 8 GB RAM. That means we will have $\frac{8GB}{32 bits}$ = $\frac{2^{33}B}{2^{2}B}$ = $2^{31}$ words.

So, the address bus will need to have 31 lines to carry 31 bit address.

In question it has been given:

A 32-bit wide main memory unit with a capacity of 1GB is built using 256 M $\times$ 4-bit DRAM chips.

It means that word width = 32 bits. Number of such 32 bit words that can fit in 1GB RAM = $\frac{2^{30}Bytes}{32 bits} = \frac{2^{30}}{2^{2}} = 2^{28}$ words. Therefore we will need 28-bits to address each word in this RAM.

256 M $\times$ 4-bit, this means that there are 256 M cells each of which contains a word of 4-bit length. Size of such D-RAM chip = 256 M $\times$ 4-bit = $2^{30}$ bits = $2^{27}$ Bytes.

Now we need to build a RAM of size 1GB = $2^{30}$Bytes using D-RAM chip of size 256 M $\times$ 4-bit = $2^{27}$ Bytes.

Clearly we will need 8 such 256 M $\times$ 4-bit D-RAM chips.