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A $32$-$bit$ wide main memory unit with a capacity of $1\;GB$ is built using $256$ $M \times 4-bit$ DRAM chips. The number of rows of memory cells in the DRAM chip is $2^{14}$. The time taken to perform one refresh operation is $50$ $nanoseconds$. The refresh period is $2$ milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is_____.
asked in CO & Architecture by Boss (18.3k points)
edited by | 4.4k views
Flying over head :p

At start it seems simple RAM concept extended but after that it went out of track for me :p

Can't even guess the answer as it is NAT Question
here it was clearly mentioned that questions on RAM wouldn't be there !!!


To prevent this, external circuitry periodically reads each cell and rewrites it, restoring the charge on the capacitor to its original level.

Refer ->

Read/Write is happening as a part of refresh operation then why is it asked for separately ?

One more doubt why all the rows can not be refreshed in one cycle ?

@VS, @Subarna Das, @Ashwin Kulkarni, @ habedo007 and @Digvijay Pandey ji. What is your opinion ?



Refreshing does not employ the normal memory operations (read and write cycles) used to access data, but specialized cycles called refresh cycles which are generated by separate counter circuits in the memory circuitry and interspersed between normal memory accesses


Chhotu During this refreshing the old(or already stored) data is read and rewritten into the cells but in ordinary read/write operation, data is read not for the purpose of restoring and "write" is to store new data into the cells.

If i am wrong then correct me.

Why do they give information about the DRAM size and which chips are used for it in such questions?

DRAM Starts from 21 minutes onwards 

hope this could help !!!

1 Answer

+39 votes
Best answer

One refresh operation takes $50ns$.
Total number of rows $= 2^{14}$

Total time to refresh all Rows $= 2^{14}\times 50\; ns = 819200 \;ns =  0.819200\;ms$
The Refresh Period is $2ms.$

$\%$ Time spent in refresh  $= \frac{Total\ time\ to\ Refresh\ all\ Rows}{Refresh\ period}*100
                                             $= \frac{0.8192ms}{2.0ms}*100$ $= 40.96\%$

$\%$ Time spent in Read/Write $= 100 - 40.96 = 59.04\%$

$= 59\%$ (Rounded to the closest Integer)


answered by Veteran (59.4k points)
edited by
Great explanation :)
All the chips are refreshed simultaneously?

@Peach yes. Take a look at this question for better understanding:

It is said that "refresh period is 2 millisecond" ie the rows get refreshed every 2 seconds, why is the time take for refresh included in the period. Please correct my interpretation about period.
In 2msec, the time given to refresh is 2^14*50 nsec and rest will be for read and write.We are just talking about time spent on read/write in 2msec only.



It is given that Refresh period is 2 ms after every 2 ms all the rows should get refreshed .

Hence ..time to refresh one row  = 2ms / # of rows ..

But here given Refresh time for row is 50nsec...

Why so...which statergy of refresh is implied here..burst or distributed ??

Bro refresh period is 2ms. It is upper limit, it means if we refresh a row now, it should be refreshed before that 2ms otherwise it would be faded. but we are refreshing all the rows in less than that time as given refresh time for a row is 50ns. So in the time remaining we could read or write.
There would be 8 chips required in total.

All of them can be refreshed in parallel and in a single row of a DRAM chip, all cells can be refreshed in parallel.

So, total refresh time should be $2^{14} \times 50\,ns$
Yes ...there is a single row of 8 dram chips.... :)

@Ayush Upadhyaya

but how to check its parallel and not serial architecture? As for total number of rows we need no.of rows per dram * no.of dram 

so how to understand? Or always take Parallel?

There we considered paralleled as per options what about NAT type as in here? How to decide?

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