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The size of the physical address space of a processor is $2^P$ bytes. The word length is $2^W$ bytes. The capacity of cache memory is $2^N$ bytes. The size of each cache block is $2^M$ words. For a $K$-way set-associative cache memory, the length (in number of bits) of the tag field is

  1. $P-N- \log_2K$
  2. $P-N+ \log_2 K$
  3. $P-N-M-W- \log_2 K$
  4. $P-N-M-W+ \log_2 K$
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Tag bits = $log (2^{P}/2^{N})+logK$ where K is a K-way set associative

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