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The instruction pipeline of a RISC processor has the following stages: Instruction Fetch $(IF)$, Instruction Decode $(ID)$, Operand Fetch $(OF)$, Perform Operation $(PO)$ and Writeback $(WB)$, The $IF$, $ID$, $OF$ and $WB$ stages take $1$ clock cycle each for every instruction. Consider a sequence of $100$ instructions. In the $PO$ stage, $40$ instructions take $3$ clock cycles each, $35$ instructions take $2$ clock cycles each, and the remaining $25$ instructions take $1$ clock cycle each. Assume that there are no data hazards and no control hazards.

The number of clock cycles required for completion of execution of the sequence of instruction is _____.
edited | 2.5k views
+4

For 100 instructions,

first 40 instructions are taking 3 cycles in PO phase. So first instruction will compete after 7 clock cycles and second instruction will complete after 10 clock cycles and so on...It is like an AP

7,10,13,...... up to 40th terms

So last term = 7 + 39 *3 = 124

first 40 instructions will be complete after 124 clock cycles.

For next 35 Instructions

41st instruction will complete after 126th clock cycle and 42nd instruction will complete after 128th clock cycle and so on...

126,128,.....up to 35th terms

So last term = 126 + 34*2 = 194

Next 35 instructions will be complete after 194 clock cycles.

For the remaining 25 instructions,

76th instruction will be complete after 195th clock cycle and 77th instruction will be complete after 196th clock cycle and so on...

195,196, 197, .....up to 25 term

So last term = 195 + 24 *1 = 219

hence, overall 100th instruction will be complete after 219 clock cycles...

Another way:

There are 100 Instructions out of which first instruction will take complete time, I mean (1 cycle for IF, 1 cycle for ID,1 cycle for OF, 3 cycles for PO and 1 cycle for WB) , So first instruction will take 7 clock cycles and remaining instructions will depend upon how much each individual instruction spending time in PO stage. Hence time would be:

7 cycles(for First instruction) + (40-1) * 3 + 35 *2 + 25*1 = 219 clock cycles..

Total Instruction $= 100$
Number of stages $= 5$
In normal case total cycles $= 100 +5 -1 = 104$ cycles

Now, For PO stage $40$ instruction takes $3$ cycles, $35$ takes $2$ cycles and rest of the $25$ takes $1$ cycle.
That means all other stages are perfectly fine and working with $CPI$ (Clock Cycle Per Instruction)$= 1$

PO stage:
$40$ instruction takes $3$ cycles i.e. these instructions suffering from $2$ stall cycle,
$35$ instruction takes $2$ cycles i.e. these instructions suffering from $1$ stall cycle,
$25$ instruction takes $1$ cycles i.e. these instructions suffering from $0$ stall cycle,

So, extra cycle would be $40*2 + 35*1 + 25*0 = 80+35 = 115$ cycle.

Total cycles = $104 + 115 = 219$
edited
+1

25 instruction takes 3 cycles,  i.e. these instructions suffering from 0 stall cycle,

Sir, small typo. It should be 25 instructions take 1 cycle,  i.e. these instructions suffering from 0 stall cycle,

+1
Corrected :-)
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Thanks sir @DigvijayPandey sir small type mistake  So extra cycle would be 40*2+35*1+25*0=80+35=115, just change sir 20 to 25 , absolutely best answer just removing already done 1 cycle used earlier in total pipeline calc
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sir in pipelining cycle time of slowest stage is taken as a common cycle time of all other stages of the instruction .

then why here you had applied structural hazard concept at perform operation stage and stalled for two cycle time instead of taking slowest stage cycle time as common cycle time .
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nice approach digvijay sir
Total Instruction =100
Instruction Fetch (IF). Instruction Decode (ID). Operand Fetch (OF), and Write back (WB) performed in 1 cycle.
PO stage:
40 instructions takes 3 cycle
35 instructions take 2 cycles
25 instructions take 1 cycle
Average number of cycles required is = (40 x 3+35 x 2+25 x 1)/100 = 2.15 cycles.
On an average first instruction completed in 1+1+1+1+2.15 cycles = 6.15;
Remaining 99 instruction will takes 99 × 2.15 = 212.85 cycles
Total number of cycles is 6.15+212.85 = 219 cycles.
We have 100 instructions.We only focus on PO stages.Becoz of pipeline,instructions execute like this...

First instruction takes 7 Clock cycles.

2nd to 40th instructions PO stages takes=39*3 clock cycles.

41th to 75th instructions PO stages takes=35*2 clock cycles.

76th to 100th instruction PO stages takes=25*1 clock cycles.

So, total=7+(39*3)+(35*2)+(25*1).

219 clock cycles required.
edited
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it's perfect. Thank you sir.
Consider it like a counting problem :

There are total (40*3 + 35*2 + 25*1 ) 'individual' PO stages and each 'individual' PO stage will take one clock cycle. Also, the initial filling of the pipeline will require 3 'extra' clock cycles of IF, ID and OF and the last clock cycle of the pipeline will always be a WB stage.

Also, since there is NO data hazard or control hazard, the IF, ID, OF and WB stages will fit in the pipeline without causing any stalls. So, the only hazard possible is due to PO stage - so, one clock cycle for each PO stage.

So, total clock cycles required = No. of clock cycles for PO stage + Initial filling of Pipeline + one last cycle for WB stage = 215 + 3 + 1 = 219 clock cycles.