#cache misses

Question

Consider a direct mapped cache of size 4 lines with line size 4 bytes.if following memory address are requested ,how many

compulsory,conflict and capacity misses are there respectively??

0,4,256,4,268,4,8,0,256,4

Comments

Compulsary misses are 5 because there are 5 unique requests.
since it is direct mapped cache so every request will map to line number 0 because every request is multiple of 4.
because of which any time there will always be 3 remaining empty lines. So capacity misses are 0.
Conflict misses are 5.
1st conflict miss = 4th request
2nd conflict miss = 6th request
3rd conflict miss = 8th request
4th conflict miss = 9th request
5th conflict miss = 10th request

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given reference is memory address reference,it is not memory block address so how all request is  mapped to line 0??

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Answer 1

Yes, given are addresses and not memory blocks.

PA size = 10 bits ( highest memory address is 268 for which we need 10 bits to represent) 

#lines = 4 ( 2 bits)

WO = 4 B ( 2 bits )

Tag = PA - ( line + WO) = 10 - ( 2+2) = 6.

       MEMORY ADDRESS        LINE NO     MISS TYPE

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0      - 0 0 0 0 0 0 0 0 0 0             0 0              COMPULSORY

4      - 0 0 0 0 0 0 0 1 0 0             0 1              COMPULSORY

256 - 0 1 0 0 0 0 0 0 0 0             0 0              COMPULSORY

4      - 0 0 0 0 0 0 0 1 0 0             0 1               HIT

268 - 0 1 0 0 0 0 1 1 0 0              1 1              COMPULSORY

4      - 0 0 0 0 0 0 0 1 0 0             0 1               HIT

8      - 0 0 0 0 0 0 1 0 0 0             1 0               COMPULSORY

0      - 0 0 0 0 0 0 0 0 0 0             0 0               CONFLICT

256 - 0 1 0 0 0 0 0 0 0 0             0 0               CONFLICT

4      - 0 0 0 0 0 0 0 1 0 0             0 1               HIT

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COMPULSORY MISSES:: 5

CONFLICT MISSES        ::  2

CAPACITY MISSES        ::  0

( CAPACITY MISSES HAPPEN ONLY IN CASE OF FULLY ASSOCIATIVE CACHE WHERE CONFLICT MISS CAN NEVER OCCUR) 

Comments

bhai ye bat galat pata hai tumko capacity miss also occur in Direct map cache as well as set asso cache

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read here

https://gateoverflow.in/69118/difference-between-compulsory-miss-conflict-miss-capacity

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@Tuhin ,to represent 268 , minimum bits should be 9 na...you have used WO(word offset) here..I think it should be cache line offset or cache block offset bcoz to represent 4B line size ,we need 2 bits in byte addressable memory..word offset means min. no. of bits to represent word size..  and in the given link no where is written that  CAPACITY MISSES HAPPEN "ONLY" IN CASE OF FULLY ASSOCIATIVE CACHE..

Please correct me if I am wrong..