Five stages:
(IF), instruction decode and register fetch (ID/RF),
instruction execution (EX),
memory access (MEM), and register writeback (WB)
P old design:
with stage latencies $\text{1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns}$
$\text{MAX( 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns) = 2.2nsec}$
AVG instruction execution time is
$\text{Tavg=(1+no of stalls$\times $branch penality)$\times $cycle time}$
$=(1+0.20\times 2)2.2$ { branch peanlity is $2$ because the next instruction
pointer at the end of the EX stage in the old design.}
$=3.08 \text{ nsec}$
Q :new DESIGN:
the designers decided to split the ID/RF stage into three stages $\text{(ID, RF1, RF2)}$
each of latency $\dfrac{2.2}{3}\text{ ns}$. Also, the $EX$ stage is split into two stages
$\text{(EX1, EX2)}$ each of latency $1\text{ ns}$.
The new design has a total of eight pipeline stages.
Time of stages in new design $=\text{{1 ns, 0.73ns, 0.73ns, 0.73ns , 1ns,1ns, 1 ns, and 0.75 ns}}$
(IF), instruction decode
register fetch (ID/RF) $\rightarrow$ further divided into $3$ ie with latency $0.73$ of each
instruction execution (EX) $\rightarrow$ further divided int $1\text{ nsec}$ of each)
memory access (MEM)
register writeback (WB)
$\text{MAX( 1 ns, 0.73ns, 0.73ns, 0.73ns , 1ns,1ns, 1 ns, and 0.75 ns) =1 nsec}$
AVG instruction execution time is
$\text{Tavg=(1+no of stalls$\times $branch penality)$\times $cycle time}$
$=(1+0.20\times 5)1$ { branch penalty is $5$ because the next instruction pointer
at the end of the $EX2$ stage in the new design.}
$=2 \text{nsec}$
final result
$\dfrac{P}{Q}=\dfrac{3.08}{2}=1.54$