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The above synchronous sequential circuit built using JK flip-flops is initialized with $Q_2Q_1Q_0 = 000$. The state sequence for this circuit for the next $3$ clock cycles is

1. $001, 010, 011$
2. $111, 110, 101$
3. $100, 110, 111$
4. $100, 011, 001$
edited | 3k views
+1
Equations will be :

Q2n = Q1'Q2' + Q0'Q2

Q1n = Q2Q1'+Q2Q1 =>  Q2

Q0n = Q1+Q0

Initial State

Input

Next State

Q2

Q1

Q0

J2

K2

J1

K1

J0

K0

Q2'

Q1'

Q0'

0

0

0

1

0

0

1

0

1

1

0

0

1

0

0

1

0

1

0

0

1

1

1

0

1

1

0

0

0

1

0

1

1

1

1

1

∴ Option C

selected by

JK ff truth table---

 j k Q 0 0 Q0 1 0 1 0 1 0 1 1 Q0’

Initially Q2Q1Q0=000 Present state FF input                   Next state

 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 Q2 Q1 Q0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 0 0 1 1 1 0 1 1 0 0 0 1 0 1 1 1 1 1

So ans is ( C) part.

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Can u please tell me if j2 and k2 are 1 and 0 then how j1 becomes 0.....it means 1 0 gives 0 as output in jkff....????!??!

I didnt get it plz calrify it... .???
0
@k.eswar prasanth

Prasanth,it is an asynchronous counter. so initially when q2,q1,q0 is 000 then

1) J2 gets it input from q0' which is 1,K2 gets from Q0 which is 0

2) J1 gets it input from Q2 which is still 0 and similarly K1 gets from q2' which is 1

because it is asynchronous counter and each ckt is having its own clock pulse so all are working at the same time. So,when J2K2 is changing working(means changing its o/p) by that time J1K1 and J0K0 is also functioning based on previous input.

This describes the difference between asynchronous ckt and synchronous ckt(where on ff o/p is in/p to another)

0
Thank you divya how can i know the circuit is synchronous or asynchronous plzz suggest me good book for sequential circuits....

Also in question it is mention "the above Synchronous sequential......
0
In synchronous counter, all the flip-flops connected in the circuit are triggered by a common pulse signal and hence change states simultaneously, whereas, in an asynchronous counter, the external input pulse triggers only the first flip-flop and and its output triggers the next, whose output again triggers the third and so on. As such, in an asynchronous counter, the flip-flops change state not simultaneously but serially, one after another, triggered by the output of the previous flip-flop.

For this topic you can refer floyd book for digital electronics. From page no 304 we have counter topic.
0
Yes now it is clear thank you very much.....
+1
@bikram sir

Here we saw that the clock is acting simultaneously on all flip flops it is working like synchronous ckt, but the above comments are discussing it as an asynchronous ckt.

So is it sync or async as there thing missing in ckt from both type of definition. To be sync. the clock should be attached to all and to be async they should be connected to one another outputs, but while solving like async i.e first taking the output of 1st flip flop and the use it for second doesn't give correct answer while if solve simultaneously all of them then option c is coming as an answer. It difficult for me to judge to put it in which of the category.
+1

bhuv

It is Synchronous circuit.

In synchronous counter, all the flip-flops connected in the circuit are triggered by a common pulse signal and hence change states simultaneously,

so when u solve this problem ,  solve simultaneously all of them then option c is coming as an answer . That means it is synchronous .

0
@bikram sir

Yes, thnx for confirming. They discussed above that it is asynchronous. But I too have opinion that it is synchronous.

But is it not a necessary condition that a common clock pulse connected to all flip flops must be there, but this is achieved here indirectly. Is there any other variations possible like this to be synchronous ckt.
+1

bhuv

See the question, it says "The above synchronous sequential circuit .."

so that means we have to assume that this circuit is synchronous and proceed accordingly..

as simple as possible

Although given answer is correct one thing worth to be noted here as it's "asynchronous circuit" and given "sign" of clock plus (-o>) which is "negative level trigger" {1-->0}
So when Q2 value change form 1-->0 Q1 gets complemented
0
it's synchronous

option c

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