27 votes 27 votes The above synchronous sequential circuit built using JK flip-flops is initialized with $Q_2Q_1Q_0 = 000$. The state sequence for this circuit for the next $3$ clock cycles is $001, 010, 011$ $111, 110, 101$ $100, 110, 111$ $100, 011, 001$ Digital Logic gatecse-2014-set3 digital-logic circuit-output normal + – go_editor asked Sep 28, 2014 • edited Jun 4, 2021 by Arjun go_editor 17.6k views answer comment Share Follow See all 4 Comments See all 4 4 Comments reply Punit Sharma commented Dec 3, 2018 reply Follow Share Equations will be : Q2n = Q1'Q2' + Q0'Q2 Q1n = Q2Q1'+Q2Q1 => Q2 Q0n = Q1+Q0 7 votes 7 votes smsubham commented Dec 9, 2019 reply Follow Share $Q_{ON} = Q_{1}Q_{0}' + Q_{0}Q_{0} = Q_{1}Q_{0}' + Q_{0} = (Q_{1}+Q_{0}) (Q_{0}' + Q_{0}) = Q_{1} + Q_{0}$ 0 votes 0 votes Lakshman Bhaiya commented Jan 1, 2020 reply Follow Share $Q_{Next} = J\:\overline{Q} + \overline{K}\: Q$ 3 votes 3 votes Hira Thakur commented Nov 1, 2023 i reshown by Hira Thakur Nov 1, 2023 reply Follow Share $J_2=\bar Q_1,K_2=Q_0,J_1=Q_2,K_1=\bar Q_2,J_0=Q_1,K_0=\bar Q_0$ it is a mod 5 counter whose sequence is :$000\rightarrow100\rightarrow110\rightarrow111\rightarrow011$ 0 votes 0 votes Please log in or register to add a comment.
Best answer 46 votes 46 votes Option C Gate_15_isHere answered Jan 28, 2015 • edited Jun 4, 2021 by Arjun Gate_15_isHere comment Share Follow See all 0 reply Please log in or register to add a comment.
17 votes 17 votes as simple as possible Swami patil answered Jan 13, 2018 Swami patil comment Share Follow See 1 comment See all 1 1 comment reply Abhineet Singh commented Nov 10, 2020 reply Follow Share perfect solution 0 votes 0 votes Please log in or register to add a comment.
6 votes 6 votes JK ff truth table--- j k Q 0 0 Q0 1 0 1 0 1 0 1 1 Q0’ Initially Q2Q1Q0=000 Present state FF input Next state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 Q2 Q1 Q0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 0 0 1 1 1 0 1 1 0 0 0 1 0 1 1 1 1 1 So ans is ( C) part. Regina Phalange answered Apr 1, 2017 Regina Phalange comment Share Follow See all 9 Comments See all 9 9 Comments reply Show 6 previous comments Bikram commented Aug 24, 2017 reply Follow Share @ bhuv It is Synchronous circuit. In synchronous counter, all the flip-flops connected in the circuit are triggered by a common pulse signal and hence change states simultaneously, so when u solve this problem , solve simultaneously all of them then option c is coming as an answer . That means it is synchronous . 4 votes 4 votes bhuv commented Aug 24, 2017 reply Follow Share @bikram sir Yes, thnx for confirming. They discussed above that it is asynchronous. But I too have opinion that it is synchronous. But is it not a necessary condition that a common clock pulse connected to all flip flops must be there, but this is achieved here indirectly. Is there any other variations possible like this to be synchronous ckt. 0 votes 0 votes Bikram commented Aug 25, 2017 reply Follow Share @ bhuv See the question, it says "The above synchronous sequential circuit .." so that means we have to assume that this circuit is synchronous and proceed accordingly.. 3 votes 3 votes Please log in or register to add a comment.
0 votes 0 votes Although given answer is correct one thing worth to be noted here as it's "asynchronous circuit" and given "sign" of clock plus (-o>) which is "negative level trigger" {1-->0} So when Q2 value change form 1-->0 Q1 gets complemented Prateek kumar answered Dec 22, 2017 Prateek kumar comment Share Follow See 1 comment See all 1 1 comment reply Punit Sharma commented Dec 3, 2018 reply Follow Share it's synchronous 4 votes 4 votes Please log in or register to add a comment.