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Consider two cache organization: the first one is 32 kB 2-way set associative with 32 B block size. The second one is of the same size but direct mapped. The size of an address is 32 bit in both cases. A 2 to 1 multiplexer has latency of 0.6 ns while a k-bit comparator has a latency of k/10 ns   the hit latency of set associative organization is h1 while that of the direct mapped one h2

Q.12 th value of h1 is

 A. 2.4ns        b. 2.3 ns

c. 1.8 ns     d. 1.7 ns

Q.13 the value of h2 is

A. 2.4 ns   b 2.3 ns     c. 1.8ns    d. 1.7 ns




My answers are as-

12. Op-a

Multiplexer latency+ comparator latency

= 0.6 + 18/10 as for set associative k=18 bit(tag bit)

= 2.4 ns


For 13. Op-d

Only comparator latency =k/10

=17/10 = 1.7 ns

Am i doing any thing wrong???

in CO and Architecture
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For this question, ur both answers r correct..

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