Virtual Memory

Question

I have some doubt please listen me out an point where I am wrong if i am wrong..

Let's say  I have a physically addressed cache, a TLB and 2 level page table memory.(page table present in memory)

Cpu generated a Logical address then firstly by the help of MMU we lookup in TLB two case can arrive :--

1. TLB hit :-

         Now we will access that page we will check cache first because that page can be in cache if cache miss then  2* memory access because there are  two level page table.

2. TLB miss :-

         Since page table is in main memory we will access main memory directly not cache here right? Or will it check in cache first for the presence of page?

Comments

Yes, they are doing it separately. You can follow the comment below the question.

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Thanku @Jason. Now my Last and Final Question:- 

Whenever we talk about the cache access its always sequential by default instead of parallel one right?

Just like in  Question :   https://gateoverflow.in/788/gate2003-78  they have done  0.9*(1) + 0.4*(1+10)  thats ok.

But we also do have a formula.Tavg = t1 + (1-h)*(t1 + t2),this formula isnt applied in above question,but unlike in this Question : http://gateoverflow.in/2778/gate1996_26.

So please tell when to apply which one?    

Thanks for the Help :)  Hope to see your answer Soon..

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https://gateoverflow.in/130206/co-hierarchical-vs-simultaneous-memory-organization

Refer this to get clarity over the concept of cache access.