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Consider a synchronous bus that operates according to the timing diagram in figure. The address transmitted by the processor appears on the bus after 4 ns. The propagation delay on the bus wires between the processor and different devices connected varies from  1 to 5 ns, address decoding takes 6 ns, and address device takes between 5 and 10 ns to place the requested data on the bus. The input buffer needs 3 ns. set up time. What is maximum clock speed at which this bus can operate?

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in one cycle address is placed in the bus and in next cycle data transfer happen.

To place the address total time required= address transmitted by the processor appears on the bus + propagation delay on the bus wires between the processor and devices

                                                              =4ns + 5ns

                                                             = 9ns

For data transfer total time required = address decoding time + to place the requested data on the bus + input buffer needs set up time

                                                         = 6ns + 10ns + 3ns

                                                         = 19ns

as data transfer total time > time required for placing address,so we have to set clk time as 19ms.

so clk frequency will be $\frac{1}{19ns}$ = 52.63 MHZ
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since u ve nt mentioned Slave Ready signal asserted by slave,so i assume that data transfer spans a single clock cycle.so to accommodate the varying speeds of different  devices connected to the bus we need to calculate delays based on slowest device.

  4 ns(address transmitted by the processor ) + 5 ns(worst propagation delay ,both side ) +  6 ns(address decoding )+10 ns(place the requested data on the bus )+ 3 ns.( set up time)=28ns clock cycle

Maximum clock speed = 35.7 MHz

correct me if wrong
edited by

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