since u ve nt mentioned Slave Ready signal asserted by slave,so i assume that data transfer spans a single clock cycle.so to accommodate the varying speeds of different devices connected to the bus we need to calculate delays based on slowest device.
4 ns(address transmitted by the processor ) + 5 ns(worst propagation delay ,both side ) + 6 ns(address decoding )+10 ns(place the requested data on the bus )+ 3 ns.( set up time)=28ns clock cycle
Maximum clock speed = 35.7 MHz
correct me if wrong