Q26 ch-5 M_E workbook

Question

suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memory is 100 cycles the hit time of the L2 cache is 10 clock cycles.the hit time of the L1 cache is 1 clock cycle.

Ques. if there are 1.5 memory references per instruction. What is the average stall cycles per instruction

a. 3.4 cycles    b. 3.5 cycles        c. 3.2 cycles      d. 3.6 cycles

My work-

miss rate of L2 is  0.02 (global)     and 0.5(local)

miss rate for L1 is 0.04

miss penalty for L1 is 60 cycles

for average stall cycles per instruction = (memory reference per instruction) x (miss rate) x (miss penalty)

right??

so which miss rate and miss penalty should i put here?

Comments

No.of memory reference per inst : 1.5

Miss rate of L1 : 0.04

Miss penalty of L1 : 60 (hit time L2 + miss rate L2*miss penalty L2)

So AVG stall per inst = 1.5*0.04*60=3.6


NOTE: CPU take words from L1 cache, so miss rate and penalty of L1 is considered. As we can see miss penalty of L1 has already included the miss penalty of L2.

Answer 1

1.5 memory references for 1 instruction...

1000 memory references for 2000/3 instruction

no of stall cycles=miss in l1*miss penalty in L1+miss in L2*miss penalty in L2

                              =40*10+20*100

                              =2400

so avg no of stalls per instruction=2400/(2000/3)

                                                            =3.6

Comments

hit time of the L2 cache is 10 clock cycles means miss penalty from the L1 cache to L2 cache is 10 clock cycles .

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Can you please explain how to calculate average memory access time in this question.

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what do you mean by miss penalty from the L2 cache to memory?

does it incudes block transfer from MM to L2 and then from L2 to L1? or from MM to L2 only?

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Here total 40 misses in L1 cache....from that 40 misses , 20 misses in L2 cache....that means total 20 memory reference to main memory and 20 memory reference to L2 cache........otherwise all correct.....correct me...if i'm wrong

Answer 2

Answer 3.6 clock cycles