GATE CSE 2011 | Question: 21

Question

Consider a hypothetical processor with an instruction of type $\text{LW  R1, 20(R2)}$, which during execution reads a $32\text{-bit}$ word from memory and stores it in a $32\text{-bit}$ register $\text{R1}$. The effective address of the memory location is obtained by the addition of a constant $20$ and the contents of register $\text{R2}$. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?

• A. Immediate addressing
• B. Register addressing
• C. Register Indirect Scaled Addressing
• D. Base Indexed Addressing

Comments

Purple

It's not Register Addressing because we don't use Offset in Register Addressing.

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option D) Base indexed addressing

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THE WORD IN MEMORY IS THE GAME CHANGER

HENCE IT IS BASED INDEXED ADDRESSING MODE

AS DURING DYNAMIC LINKING/LOADING, THE BASE AND RELOCATABLE REGISTER WILL COME INTO ACTION

AND THE ADDRESS GENERATED BY THE CPU WILL BE INCREMENETED BY SOME VALUE AT THE RUNTIME.

HOW BEAUTIFULLY MEMORY PROTECTION OF OS IS LINKED WITH ADDRESSING MODES CONCEPT OF COA

THIS REMINDS ME OF THE FACT THAT HOW IMPORTANT IS READING THE QUESTION VERY VERY CAREFULLY WORD BY WORD

OMG. IITS

Answer 1

LW R1 , 20(R2)

options A,B are anyway out of the context.

first of all in such writings 2 symbols directly means indirect , 1) @  2) (  );

2nd of all in base addressing or based indexed addressing we do not I REPEAT we do not use the base value like this.

i dont know if option C is correct or not..

but D can't be the answer...

in based indexed addressing we must use 2 registers... giving 20 directly is not fulfilling the rules.

*****Wikipedia*****

(Effective address = contents of specified base register + contents of specified index register)

 

*****geeksforgeeks*****

 

Based Indexed Addressing: The operand’s offset is sum of the content of a base register BX or BP and an index register SI or DI.

Example: ADD AX, [BX+SI]