#sample_test_iitk

tapzo asked Apr 15, 2018

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An address sequence S experiences 100 compulsory cache misses. The sequence S experiences 500 misses when it is passed through a 32 KB fully-associative cache. The sequence S experiences 1000 misses when it is passed through a 32 KB 8-way set-associative cache. The number of conflict misses that the sequence S experiences when it is passed through a 32 KB 8-way set-associative cache is ___________

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tapzo asked Apr 15, 2018

tapzo

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rahul sharma 5

commented May 5, 2018

@gauravkc ,your definition is correct. Can we apply this in current problem?

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gauravkc

commented May 5, 2018

I'm confused. Shouldn't it depend on address sequence?

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srestha

commented May 5, 2018

no not possible, i think

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