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In a two-level cache system, the access times of L1 and L2 are 3, 10 clock cycles respectively. The miss penalty from the L2 cache to main memory is 20 clock cycles. The miss rate of L1 cache is thrice that of L2. The average memory access time(AMAT) of this cache system is 4 cycles. The miss rates of L1 and L2 respectively are:
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You formed wrong equation as miss rate can never be negative

+1 vote
L2 miss rate= 0.0247

L1 miss rate=3*0.0247

http://ece-research.unm.edu/jimp/611/slides/chap5_2.html
edited
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can you elaborate how you come up with answer
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average memory access time = L1 cache always accessed+ Probability of miss in cache L1 * time to access L2+ Probability of miss in L1 cache * Probability of miss in L2 cache * time to access main memory
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@sonveer I am getting a different answer. ML1= 0.705 ML2=0.235

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+1

UPDATED -
Hierarchical Access should be assumed.

AMAT = T1 + M1* Miss Penalty1 Miss Penalty1 = T2 + M2* Miss Penalty2 Miss Penalty2 = T3
H1 = Hit rate of Level 1 cache.
H2 = Hit rate of Level 2 cache.
M1 =Miss rate of Level 1 cache.
M2 =Miss rate of Level 2 cache.
T1= Access Time of Level 1 cache.
T2= Access Time of Level 2 cache.
T3= Miss Penalty of Level 2 cache

https://gateoverflow.in/118371/gate2017-2-29

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@Soumya , your equation is correct but I m getting L2 miss rate = 0.0313

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I have used :-

AMAT = T1 + M1(T2 +M2*Miss penalty of L2)

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ankit
There is a slight difference in our formula. Check again.
I assumed simultaneous access and you assumed hierarchical.

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yeah ,you are right ..I have used hierarchical memory access..
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@Soumya

why u used simulteneous access here?
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ankit , srestha   Hierarchical access should be assumed here.
Reference - https://gateoverflow.in/118371/gate2017-2-29

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yes ..but still I don't know when to use which memory access..  if someone write  some points about how to identify which memory access we have to use from the question then it will be good for us. I asked this question previously https://gateoverflow.in/179647/memory-access but sometimes I get from the question and sometimes I don't identify which memory access we should have to use..

+1

ankit
What I observed in previous year questions is -

1.If only "Access Times"are given like in this question - then hierarchical access is considered.
2. If hit time, miss time terminologies are used  - then simultaneous access is considered.
3. It "Ignore the search time" like this is mentioned in the question then simultaneous access is considered irrespective of the terminologies(access time, hit time, miss time etc).

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yes u r right..thank you !
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It's quite convincing too... :)
Access time belongs to the single type of memory only.
So hierarchical access makes sense.
First access level 1 cache. If found - access it, If data not found then access level 2 cache and so on.

If hit time or miss time is given - means we don't have to worry about the type of memory access.
It's simply - hit rate * hit time + miss rate * miss time

If given that search time is ignored. This implies simultaneous access.
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Hey @ankit @soumya , why didn't you use

AMAT = H1T+ M1(H2T2 +M2*Miss penalty of L2)

because according to hamacher (Edition 5th, P. No 332, Ex. 5.2),

AMAT = hC + (1 - h)M                    where, h = hit rate, C = access time in cache, M = Miss penalty

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Hi Bittu ,  you are not adding the  access time of previous levels to get the memory access time of next levels.

In Hierarchical Memory Access model , We go level by level means we have to add the memory access time of all previous levels if we have gone through those memory levels.

Suppose ,

$T_{1}$ = Level 1 cache access time

$T_{2}$ = Level 2 cache access time

$T_{3}$ = Miss Penalty from Main Memory  to Level 2 cache to get data back in level 2 cache

Now ,

AMAT = $H_{1} \; *\; T_{1} \; + \; (1-H_{1})*\;[H_{2}\;*\;(T_{1}+{T_{2}}) + (1-H_{2})\;*\;(T_{1}+T_{2}+{T_{3}})]$

$(Or)$

AMAT = $T_{1} \; + \; (1-H_{1})*\;[ {T_{2}} + (1-H_{2})\;*\;{T_{3}}]$

Both equations are same. when you expand $1^{st}$ equation and simplify it then you will get the $2^{nd}$ equation.

@Soumya , Please correct me if anything is wrong in my explanation.
+1

Thanks, @ankit. You're right. I found this pdf after I wrote my comment https://www.cse.iitk.ac.in/users/karkare/courses/2011/cs220/notes/Module22Handout.pdf. It has the same explanation which you provided. I guess Hamacher book missed few details which could've provided more clarity. Thanks again.

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@ankit seems correct :)
Just 1 thing-

T3 = Miss Penalty from Main Memory  to Level 2 cache to get data back in level 2 cache

Did you mean the same?  -
If there is a miss in $L_2$ cache then the desired word is fetched directly from MM and MM block containing the desired word is stored in L1 and L2 cache at the same time?

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@Soumya , No , I meant desired word will be stored in L2 cache only after miss penalty from Main Memory.

Here , Miss Penalty means :-

1) If there is a miss in $L_{2}$ cache then it will access Main Memory. So, Miss Penalty includes access time of Main memory $+$ data transfer time to replace some cache block of $L_{2}$ cache by desired Main Memory block using some cache replacement policy.

$(Or)$

2) If there is a miss in $L_{2}$ cache then it will access Main Memory. So, Miss Penalty includes access time of Main memory $+$ data transfer time to replace some cache block of $L_{2}$ cache by desired Main Memory block using some cache replacement policy + data transfer time to replace some cache block of $L_{1}$ cache by desired cache block of $L_{2}$ cache. So that processor will find data easily in $L_{1}$ cache.

According to you, which one is correct definition of Miss Penalty ?