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In a two-level cache system, the access times of L1 and L2 are 3, 10 clock cycles respectively. The miss penalty from the L2 cache to main memory is 20 clock cycles. The miss rate of L1 cache is thrice that of L2. The average memory access time(AMAT) of this cache system is 4 cycles. The miss rates of L1 and L2 respectively are:

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L2 miss rate= 0.0247

L1 miss rate=3*0.0247

http://ece-research.unm.edu/jimp/611/slides/chap5_2.html
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