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I know the Concept of Binary ripple carry adder but i don't understand about the delay.I know that the output wont be generated until carry is propagated.So how to find The actual delay which will be there and how to determine which input will take max delay ?

I cant solve the Questions involving the calculations on finding Delay.Can anybody explain how to do it using an Example ? Please
asked in Digital Logic by Active (4k points)
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2 Answers

+1 vote

 @Na462 i hope it may help you

answered by Active (4.8k points)
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Binary ripple carry adder:-

To calculate delay find the longest path from the carry in to carry out

Taking 4-bit ripple carry adder:-

$sum=a0\Theta b0\Theta cin$

$carry out=a0*b0+(a0\Theta b0) * cin$

Now you can calculate a0 exor b0= $a0\Theta b0$ and a0*b0 => delay of maximum (Exor gate, AND) as both are working parallely 

after getting a0 exor b0 find ( $a0\Theta b0$ ) * cin => delay AND gate delay.

And now perform one OR operation to get carry out

$carry out=a0*b0+(a0\Theta b0) * cin$ =>> delay OR gate

First stage delay => Exor+AND+OR

now in second stage computing a1 and b1 sum,

a1 exor b1 and a1 and b1 is parallely computed as it is independent of previous stage. so delay in second stage is basically :- AND to compute ( a1 exor b1 ) AND previous stage carry + OR to compute cout.

Second stage delay =>> AND+OR

similarly Third stage delay =>> AND+OR

Fourth stage delay ==> AND+OR

Total delay= one EXOR delay + 4(AND+OR)

answered by Active (3k points)
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Actually i just completed studying digital logic and started to solve the Questions,so its becoming little bit hard to understand your solution though its correct.Can you please explain by taking a real example and solve it Please. and thank you for your valuable reply

Sorry sir for such reply :(
0
NO, its okey i will solve previous year gate question based on that. You please read morris mano.
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Yes sir i studied from morris mano only and there also it was written that total propagation time is equal to the propagation delay of a typical gate times the number of gate levels in the circuit ----->(As far as i understand) means delay taken by number of gates in a level * number of gate level in the circuit am i right ?

for a n bit  parallel adder there are 2n gate levels for the carry to propagate through ---> This was little bit unclear So kindly explain in sir.

But still i cant get a clear and satisfactory solved example for calculating the Delay so that i can fully understand it.


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