Q-27 ch-4 pipeline

Question

Consider 2 pipeline with the following specification

Stall cycle for memory	pipeline	no. Of stage	memory
1	A	k	single port
0	B	k	dual port

The pipeline allows all instructions except memory based instructions. If 2 memory operations can not be done in same clock. The penalty is 1 clock. Let there are 20% memory instructions obtain S_a/S_b

A. 0.833     b.  0.53      c.  0.94     d. 0.24

Comments

what is the meaning of saying

If 2 memory operations can not be done in same clock. The penalty is 1 clock.

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let CPI = 1ns.

Pipeline A 

No. of Stages = k stages

It is given in question that Pipeline A uses Single Port Memory so in order to serve 2 memory request there will be a penalty of 1 clock.

Total no. of memory request = 20 % = 0.2 

Time taken to serve memory request = 0.2* 1 ns= 0.2 ns

So to serve an instruction we need 1 + 0.2(overhead)= 1.2 ns

Sa = k stages /1.2 ns

Pipeline B

No. of Stages = k stages

It is given in question that Pipeline B uses Dual Port Memory so in order to serve 2 memory request there will be no penalty.

Total no. of memory request = 20 % = 0.2 

Time taken to serve memory request = 0.2 * 0 ns = 0 ns

So to serve an instruction we need 1 + 0.0(overhead)= 1.0 ns

Sb = k stages /1.0 ns

Thus, Sa/Sb = (k / 1.2 ns) * (1 ns/k) = 1/1.2 =  .0.833

Answer 1

speed Sa=k/1+0.2 speed Sb=k Sa/Sb=1/1.2=0.833

Comments

can u plz explain ur ans?

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Please explain how you got the answer