(common data q-30_31)
A pipelined processor uses a 4- stages instruction pipeline with the following stages. Instructions fetch (IF) , instruction decode (ID), execute (EX) and write back (WB). The arithmetic operations as well as the load and store operations arr carried out in the Ex stage. the sequence of instructions corresponding to the statement
X= ( s-r*(p+q))/t os given below:
The values of variables p,q,r,s and t are available in rhe resisters ro, r1, r2 and r4 respectively; before the execution of the instruction sequence.
Add r5,r0,r1 r5 <- r0+r1<br />
Mul r6,r2,r5 r6 <- r2*r5<br />
Sub r5,r3,r6 r5 <- r3-r6<br />
Div r6,r5,r4 r6 <- r5 / r4<br />
Store r6,x; x <-r6<br />
Q-30 the number of read-after-write(raw), write-after-read(war) nd write-after-write(waw) de dependencies in the sequence of instructions are respectively.
A.2,2,4
b.3,2,3
c.4,2,2
d. 3,3,2
Q-31 the if,id and wb stages take 1-clock cycle each. The ex stage takes 1- clock cycle each for the add,sub and store operations and 3-clock cycles each for mul nd div operations. Operand forwarding from the ex stage to the id stage is used. The number of clock cycle required to complete the sequence of instructions is
A.10
b.12
C. 14
D. 16
(For q -31 my ans 12)
