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On a non-pipelined sequential processor, a program segment, which is the part of the interrupt service routine, is given to transfer $500$ bytes from an I/O device to memory.

        Initialize the address register
        Initialize the count to 500
LOOP:   Load a byte from device              
        Store in memory at address given by address register
        Increment the address register
        Decrement the count
        If count !=0 go to LOOP

Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.

The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires $20$ clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.

What is the approximate speed up when the DMA controller based design is used in a place of the interrupt driven program based input-output?

  1. $3.4$
  2. $4.4$
  3. $5.1$
  4. $6.7$
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AGAIN NPTEL ASSIGNMENT QUESTION
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Nptel put the gate question in assignment and not vice-versa.

The assignment is of2017 and question is of gate-2011
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1 Answer

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93 votes
 
Best answer
$$\begin{array}{llc} & \textbf{Statement} & \textbf{Clock Cycles(s) Needed} \\\hline
& \text{Initialize the address register} & \text{1} \\
& \text{Initialize the count to 500} & \text{1} \\
\text{LOOP:} &\textbf{Load}\text{ a byte from device} & \text{2}  \\
& \textbf{Store}\text{ in memory at address given by address register} & \text{2} \\
& \text{Increment the address register} & \text{1} \\ & \text{Decrement the count} & \text{1} \\
& \text{If count != 0 go to LOOP} & \text{1}  \end{array}$$
Interrupt driven transfer time $= 1+1+500\times(2+2+1+1+1) = 3502$

DMA based transfer time $= 20+500\times 2 = 1020$

Speedup $= 3502/1020 = 3.4$

Correct Answer: $A$
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Oh so in this DMA approach we don't need to increment the register or those other instructions or in other words in the DMA approach it uses 500 iterations of 2 cycles each to transfer those 500 bytes plus the 20 cycles for initialisation, am I right ?
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yes, exactly.
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Thank you, that has cleared up my doubt.
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Such a beautiful question OMG
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Answer:

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