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On a non-pipelined sequential processor, a program segment, which is the part of the interrupt service routine, is given to transfer $500$ bytes from an I/O device to memory.

        Initialize the address register
        Initialize the count to 500
LOOP:   Load a byte from device              
        Store in memory at address given by address register
        Increment the address register
        Decrement the count
        If count !=0 go to LOOP

Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.

The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.

What is the approximate speed up when the DMA controller based design is used in a place of the interrupt driven program based input-output?

  1. $3.4$
  2. $4.4$
  3. $5.1$
  4. $6.7$
asked in CO & Architecture by Veteran (112k points)
edited by | 2.6k views

1 Answer

+56 votes
Best answer
  Statement Clock Cycles(s) Needed
  Initialize the address register 1
 

Initialize the count to 500

1
LOOP:

Load a byte from device

2
 

Store in memory at address given by address register

2
 

Increment the address register

1
 

Decrement the count

1
 

If count != 0 go to LOOP

1


Interrupt driven transfer time $= 1+1+500\times(2+2+1+1+1) = 3502$

DMA based transfer time $= 20+500\times 2 = 1020$

Speedup $= 3502/1020 = 3.4$

answered by Boss (41.6k points)
selected by
+1
If count != 0 go to LOOP # will execute 501 times and total will be 3503 for ISR based approach. Though this doesn't affect the answer.
+3
No..loop runs for 500 times only..

Take count=3 .and check it runs for 3 times only..
+3
Could someone tel how are the DMA transfer time calculated ?
+11

PEKKA 

 how are the DMA transfer time calculated ?

See in question it says The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.

So DMA transfer time = 20 ( this is total nuber of clock cycles for initialization ) + 500 * 2 ( as loop will go up to 500 times as a device to memory transfer and each transfer takes 2 clock cycles ) 

0
How interrupt driven time is calculated ?
Answer:

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