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In the diagram above, the inverter (NOT gate) and the AND-gates labeled $1$ and $2$ have delays of $9$, 10 and $12$ nanoseconds (ns), respectively. Wire delays are negligible. For certain values $a$ and $c$, together with certain transition of $b$, a glitch (spurious output) is generated for a short time, after which the output assumes its correct value. The duration of glitch is:

  1. $7$ $ns$
  2. $9$ $ns$
  3. $11$ $ns$
  4. $13$ $ns$
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3 Answers

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Best answer

The output of AND gate 1 will be available at the input of OR gate after 9+10 = 19 nanoseconds but Output of  AND gate 2 will be available after 12 nanoseconds only.
So a glitch will be generated for 19-12 = 7 nanoseconds after which the output assumes its correct value. 
Option A is correct. 

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Ans will be A.(10+9)-12=7ns
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3 Comments

question is not correct I think

here given inverter ,AND gate deays

and delays given 9,10,12 ns

which one is OR gate delay?
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0
i think it's independent of OR gate delay
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0

since here OR gate delay is not given ...so take its delay as zero..

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3 votes
3 votes
  • Inverter and AND1 gate will take total of 9 + 10 = 19 ns. (one after another)
  • AND2 gate will take 12 ns.
  • before 12 ns there was no glitch(fault) as none of inputs has reached to OR
  • now at 11th ns input from AND2 gate reaches to OR and yet there is no other input to OR
  • This glitch(fault) will remain till 19th second when output of NOT-AND2 appears as input to OR
  • Then OR will operate normally 
  • so glitch was from 12th to 19th ns 19−12=7ns

option (A)

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Answer:

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