1 votes 1 votes Plz describe Which addressing mode does this following line represents and how? Index addressing mode, $X\left ( R_{1} \right )$, where $X$ is an offset represented in $2$'s complement $16$ bit representation CO and Architecture addressing-modes co-and-architecture + – srestha asked Apr 26, 2018 srestha 793 views answer comment Share Follow See all 6 Comments See all 6 6 Comments reply Show 3 previous comments srestha commented Apr 27, 2018 reply Follow Share yes, but same thing can be done in index addressing mode too how do u know , it is not index adderessing mode , and only displacement addressing mode? 0 votes 0 votes rahul sharma 5 commented Apr 27, 2018 reply Follow Share Question is asking , we have an index addressing ,and which addressing mode functionality is implemented by this index addressing mode.Can you tell me source of question or options if any? 0 votes 0 votes srestha commented Apr 27, 2018 reply Follow Share ya it is a gate question (https://gateoverflow.in/118291/gate2017-1-11) but I feel confused, how these 2 line represents displacement mode 0 votes 0 votes Please log in or register to add a comment.
3 votes 3 votes Rahul explain right, X(R1):- Here register R1 hold some base address, and X contains displacement. If you are currently executing say line 1000 and wants to jump at 750 and X will store that displacement in 2's complement forn. sonveer tomar 1 answered Apr 26, 2018 sonveer tomar 1 comment Share Follow See all 0 reply Please log in or register to add a comment.