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Consider an instruction pipeline with four stages $\text{(S1, S2, S3 and S4)}$ each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure.

What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?

  1. $4.0$
  2. $2.5$
  3. $1.1$
  4. $3.0$
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Answer is (B) 2.5

In pipeline system, Time taken is determined by the max delay at any stage i.e., $11$ $\text{ns}$ plus the delay incurred by pipeline stages i.e., $1$ $\text{ns}$ = $12$ $\text{ns}$. In non-pipeline system,

Delay = $5$ $\text{ns}$ $+$ $6$ $\text{ns}$ $+$ $11$ $\text{ns}$ $+$ $8$ $\text{ns}$ $=$ $30$ $\text{ns}$.

$\therefore$ $\text{The speedup is}$ $\frac{30}{12} = 2.5$ $\text{ns}$.

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A better way to solve would be

For non pipeline implementation, time to complete each instruction t = 5+6+11+8 = 30ns

For pipeline implementation, max duration for each stage T = 11+1 =12ns

For k instructions,

Total cycles for non-pipeline implementation = k*t

Total cycles for non-pipeline implementation = (k + n - 1)*T, where n = #stages

Consider 100 instructions

i) for non pipeline: C1 = 100 * 30 = 3000ns

ii) for pipeline: C2 = (100 + 4 -1)*12 = 103*12 = 1236ns

iii) Speedup = C1/C2 = 3000/1236 = 2.5 (approx)

Same holds true for 1000 instructions,

Hence answer is B

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