Here states q0,q1 are adding two bits when no carry is generated. q2,q3 are adding states when carry generated from previous state.
Take an example suppose -
we want to add A=110001 B= 111001
A= 1 1 0 0 0 1
B= 1 1 1 0 0 1
1 1 0 1 0 1 0
q2->q3 q1->q2 q0->q1 q1->q0 q2->q1 q0->q2
end carry is ignored hence the answer. Hope it helps!