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The main memory unit with a capacity of $4$ $\text{megabytes}$ is built using $1\text{M} \times \text{1-bit}$ DRAM chips. Each DRAM chip has $1\text{K}$ rows of cells with $1\text{K}$ cells in each row. The time taken for a single refresh operation is $100\; \text{nanoseconds}$. The time required to perform one refresh operation on all the cells in the memory unit is

1. $100$ nanoseconds
2. $100\times 2^{10}$ nanoseconds
3. $100\times 2^{20}$ nanoseconds
4. $3200\times 2^{20}$ nanoseconds

if they cheat on us they might give but they themselves declared :P read from the link
It is in syllabus, similar question was asked in GATE-2018

Mk Utkarsh  THEY CHEATED ACCORDING TO  Venkat Sai

Similar question asked in GATE 2018:

https://gateoverflow.in/204097/gate2018-23

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There are $4\ast 8 = 32$ DRAM chips to get $4\;\text{MB}$ from $1\text{M} \times \text{1-bit}$ chips. Now, all chips can be refreshed in parallel so do all cells in a row. So, the total time for refresh will be number of rows times the refresh time

$= 1\text{K} \times 100$

$= 100 \times 2^{10}$ nanoseconds

Correct Answer: $B$

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convert bit to byte
edited

@srestha No answer won't be 3200 * 2^10 and the reason is

Main memory size = 4MB =  2^22 * 1 Byte

1 Chip Size = 1 M * 1bit so convert it to byte = (1 M * 1 bit) / 8 = 2 ^ 17 * 1 Byte

Number of Chips Required :  Main Memory Size / Chip Size =  (2 ^ 22 * 1 Byte) / (2^17 * 1 Byte)  = 32 Chips

yes we have 32 chips and each chip has 2^10 rows but one thing to note is : When you refresh a particular row in a chip, the same row gets refreshed in all the other chips simultaneously so the total time : Number of rows * refreshing time of 1 row = 2^10 rows * 100 ns = 100 * 2^10 ns.

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@Piyush####  But here you are assuming those 32 chips are  in single row ...what if all 32 chips are in different rows such that 1 chip/row …..then it would be 3200*2^10……

we can also have 32 chips arranged such that 8 chips/row hence total 4 rows if word size is is considered as 8 bit..(1byte) then answer would be 4*100*2^10...

.But none of the option match hence i think we have to assume  all are in single row…

As @Bikram sir has mentioned

Each row of memory module gets refreshed at once and with each cycle we can refresh 1 row of each chip at once.

@Bikram sir ,Correct me if wrong

Doesn’t 1Mx1-bit imply 1M rows of 1-bit registers? Then why is 1K row and 1K column sepcified again? Can anyone clarify?

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