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+32 votes

The main memory unit with a capacity of $4$ $\text{megabytes}$ is built using $1M \times$ $\text{1-bit}$ DRAM chips. Each DRAM chip has 1K rows of cells with $1K$ cells in each row. The time taken for a single refresh operation is $100$ $\text{nanoseconds}$. The time required to perform one refresh operation on all the cells in the memory unit is

- $100$ nanoseconds
- $100\times 2^{10}$ nanoseconds
- $100\times 2^{20}$ nanoseconds
- $3200\times 2^{20}$ nanoseconds

+45 votes

Best answer

There are 4*8 = 32 DRAM chips to get 4MB from 1M $\times$ 1-bit chips. Now, all chips can be refreshed in parallel so do all cells in a row. So, the total time for refresh will be number of rows times the refresh time

$= 1K \times 100$

$= 100 \times 2^{10}$ nanoseconds

Reference: http://www.downloads.reactivemicro.com/Public/Electronics/DRAM/DRAM%20Refresh.pdf

Correct Answer: $B$

+8

https://en.wikipedia.org/wiki/Memory_refresh#How_DRAM_refresh_works

This wikipedia page clearly says that en entire row of DRAM is refreshed at once. So, 3200*2^20 can never be the answer.

Now, whether 3200 * 2^10 be the answer- there seems no logical reason as to why 4 different DRAM chips be refreshed in parallel. This not being in choice also proves this fact.

This wikipedia page clearly says that en entire row of DRAM is refreshed at once. So, 3200*2^20 can never be the answer.

Now, whether 3200 * 2^10 be the answer- there seems no logical reason as to why 4 different DRAM chips be refreshed in parallel. This not being in choice also proves this fact.

–1

But in geeksforgeeks they have given answer as 3200*2^20

I am getting both of the options "B" as well as "D"

"D" is the case when all are refreshed serially. So for one chip the total time taken for refresh (serially not parallel) will be 100*2^20 and for 32 such chips the total time will be 3200*2^20.

Which one of them is correct?

I am getting both of the options "B" as well as "D"

"D" is the case when all are refreshed serially. So for one chip the total time taken for refresh (serially not parallel) will be 100*2^20 and for 32 such chips the total time will be 3200*2^20.

Which one of them is correct?

+12

@rama @praveen sir and @ayushi

Yes, Here we consider all 32 chips are in a single row .

Each row of memory module gets refreshed **at once** and **with each cycle we can refresh 1 row of each chip at once.**

- For a refresh, only the row address is needed, so a column address doesn't have to be applied to the chip address circuits. [1]
- During a memory refresh cycle, all memory chips are enabled so that memory refresh is performed on every chip in the memory module
**simultaneously**[2].

Also see the problem specified in Memory Refresh Period in 2^{nd} Reference . There are 4 * 8= 32 dynamic RAM's but as all dynamic RAM's are placed in a single row so they consider only number of rows ( that is 64 ) while calculating the memory time spent on refresh. [ Almost same as this question ]

- References

- https://en.wikipedia.org/wiki/Memory_refresh#How_DRAM_refresh_works
- http://www.electronics.dit.ie/staff/tscarff/memory/dram-control.htm

Also, option D i.e. 3200×2^{20 }can not be the answer, as 1K row = 2^{10} rows , so when for one chip the total time taken for refresh 100 * 2^{10} for 32 chips it would be 32 * 100 * 2^{10 }= 3200 * 2^{10} which **NOT in option** also . In option we have 3200 * 2^{20} so Option D can not be the answer ..

Hence B is the correct Answer .

+1

Link is not working now: http://www.electronics.dit.ie/staff/tscarff/memory/dram-control.htmhttp://www.electronics.dit.ie/staff/tscarff/memory/dram-control.htm

i am attaching the pdf for the webpage herehttps://gateoverflow.in/?qa=blob&qa_blobid=12537040844512335301

0

To create a 4MB memory unit using 1Mx1-bit chips we need to have 4 rows of such chips, and in each rows 8 such chips. Now, each such chip has 1K rows of cells. So, how can we refresh all cells in parallel?

0

answer should be 32 * 100 * 2^{10 }= 3200 * 2^{10} nsec but it is not in option so we have to assume that all 32 chip rows are accessed parallely

0

The main memory unit with a capacity of 44 megabytes is built using 1M×1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row.

Each DRAM chips size is 1M X 1 bit..hence 2^ 20 word lines and 1 bit line..

So how can each DRAM chip has 1k rows of cells....?? there will be 1M rows right ??

m confused in these..please help someone

Each DRAM chips size is 1M X 1 bit..hence 2^ 20 word lines and 1 bit line..

So how can each DRAM chip has 1k rows of cells....?? there will be 1M rows right ??

m confused in these..please help someone

+2

Each DRAM chips size is 1M X 1 bit..hence 2^ 20 word lines and 1 bit line..

So how can each DRAM chip has 1k rows of cells....?? there will be 1M rows right ??

actual question given that " **Each DRAM chip has 1K rows of cells with 1K cells in each row** "

so, total cells = 1 K * 1 K = 1 M cells with each 1 bit

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