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The main memory unit with a capacity of $4$ $\text{megabytes}$ is built using $1M \times$ $\text{1-bit}$ DRAM chips. Each DRAM chip has 1K rows of cells with $1K$ cells in each row. The time taken for a single refresh operation is $100$ $\text{nanoseconds}$. The time required to perform one refresh operation on all the cells in the memory unit is

1. $100$ nanoseconds
2. $100\times 2^{10}$ nanoseconds
3. $100\times 2^{20}$ nanoseconds
4. $3200\times 2^{20}$ nanoseconds
edited | 4.4k views
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Are both ram and rom not in syllabus anymore?
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ans of this is given as 3200×220 nanosesonds  in many coaching materials.....

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memory interfacing is removed from 2016 onwards so this is out of syllabus :)

https://gatecse.in/gate-cse-2016-syllabus/

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You sure bro?
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if they cheat on us they might give but they themselves declared :P read from the link
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It is in syllabus, similar question was asked in GATE-2018
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Mk Utkarsh  THEY CHEATED ACCORDING TO  Venkat Sai

There are 4*8 = 32 DRAM chips to get 4MB from 1M $\times$ 1-bit chips. Now, all chips can be refreshed in parallel so do all cells in a row. So, the total time for refresh will be number of rows times the refresh time

$= 1K \times 100$

$= 100 \times 2^{10}$ nanoseconds

edited
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Can the chips be refreshed parallely?  In one of the book i find the solution as 3200*2^20
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https://en.wikipedia.org/wiki/Memory_refresh#How_DRAM_refresh_works

This wikipedia page clearly says that en entire row of DRAM is refreshed at once. So, 3200*2^20 can never be the answer.

Now, whether 3200 * 2^10 be the answer- there seems no logical reason as to why 4 different DRAM chips be refreshed in parallel. This not being in choice also proves this fact.
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I thought it'd be C, but then refreshing the entire row at once brings it down to 210

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"There are 4*8 = 32 DRAM chips to get 4MB from 1M × 1-bit chips" will you brief this ?

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@Arjun we are taking 32 (1M x1) DRAM in a single row ?
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did you get the answer to this question?
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Are we considering all the 32 chips in single row?
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This is not in course anymore right?
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is it not??
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ram and memory interfacing is removed I guess
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But in geeksforgeeks they have given answer as 3200*2^20

I am getting both of the options "B" as well as "D"

"D" is the case when all are refreshed serially. So for one chip the total time taken for refresh (serially not parallel) will be 100*2^20 and for 32 such chips the total time will be 3200*2^20.

Which one of them is correct?
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@rama @praveen sir and @ayushi

Yes, Here we consider all 32 chips are in a single row .

Each row of memory module gets refreshed at once and with each cycle we can refresh 1 row of each chip at once.

• For a refresh, only the row address is needed, so a column address doesn't have to be applied to the chip address circuits. [1]
• During a memory refresh cycle, all memory chips are enabled so that memory refresh is performed on every chip in the memory module simultaneously [2].

Also see the problem specified in Memory Refresh Period in 2nd Reference . There are 4 * 8= 32 dynamic RAM's but as all dynamic RAM's are placed in a single row so they consider only number of rows ( that is 64 ) while calculating the memory time spent on refresh.  [ Almost same as this question ]

• References

Also, option D i.e. 3200×220  can not be the answer, as 1K row = 210 rows , so when for one chip the total time taken for refresh 100 * 210 for 32 chips it would be 32 * 100 * 210 = 3200 * 210  which NOT in option also . In option we have 3200 * 220  so Option D can not be the answer ..

Hence B is the correct Answer .

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i am attaching the pdf for the webpage herehttps://gateoverflow.in/?qa=blob&qa_blobid=12537040844512335301

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To create a 4MB memory unit using 1Mx1-bit chips we need to have 4 rows of such chips, and in each rows 8 such chips. Now, each such chip has 1K rows of cells. So, how can we refresh all cells in parallel?
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answer should be 32 * 100 * 210 = 3200 * 210 nsec but it is not in option so we have to assume that all 32 chip rows are accessed parallely

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The main memory unit with a capacity of 44 megabytes is built using 1M×1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row.

Each DRAM chips size is 1M X 1 bit..hence 2^ 20 word lines and 1 bit line..

So how can each DRAM chip has 1k rows of cells....?? there will be 1M rows right ??

+1 vote

Following is the architecture of RAM:

$4MB = 2^2*2^20*2^3 = 2^{25} bits$

$=4*8*2^{20}*1$ , as there are 4 rows, each row contains 8 chips and each chip is of size $1M*1$

$=2^2*2^3*2^{20}*2^0 = 2^{25} bits$ . we have got equal size to $2^{25}$ bits (or) $4MB$

Now there are two answers possible,

Case 1:

if we refresh all the 4 lines one by one then total time taken is: $=4*100*2^{10}$

Case 2:

And if we refresh all the 4 lines in parallel, then  total time taken is: $=100*2^{10}$

The first is not given in the option, hence 2nd case is considered here, i.e. $=100*2^{10}$

Hence, option (B) is correct.

answered ago by Junior (985 points)

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