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The instruction pipeline of RISC processor has 200 instructions in which 100 are performing addition, 25 performing division and 75 performing multiplications, where Execution state for addition take 1 clock cycle,multiplication take 3 and division take 5. Assume pipeline has 5 stages: IF, ID, EX, MA and WB and their is no data and control hazard. The number of clock cycles required for execution of sequence of instructions are

What i was thinking :  (100+5-1)*1 + (25+5-1)*5+ (75+5-1)*3 

Am i doing wrong?

Solution with explanation of formulae being used will be welcomed.

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if all 200 instruction execute normally means at each stage every instruction take 1 clock then total no. of clocks=5(for first instruction )+199*1(remaining takes only one clock)=204.

but 100 instructions doing addition and taking 1 clock cycle ,so no stall will be create.

25 division  instructions taking 5 clock cycle so these instructions will suffer from 4 stall cycles.

75 multiplication instructions taking 3 clock cycle so these instructions will suffer from 2 stall cycles.

so  extra clock cycle=100*0+25*4+75*2=250

total cycles=250+204=454.
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454 is correct as first instruction will take all stages

make pipeline chart for few instruction of all type

( 5+99)+ (25*5)+ (75*3)=454
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Total Instruction =200
Number of stages =5
In normal case total cycles =k+n-1=5+200−1=204 cycles

Now,

There are 100 instruction performing addition and EX stage takes one clock cycle(stall =0)=100*0=0

There are 25 instruction performing division and EX stage takes 5 clock cycle(stall =4)=25*4=100

There are 75 instruction performing multiplication and EX stage takes 3 clock cycle(stall =2)=75*2=150

 Extra cycle would be 100+150= 250 cycle.

Total clock cycles=250+204=454 cycles
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