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A micro-instruction format has micro-ops field which is divided into three subfields $F1$, $F2$, $F3$ each having seven distinct micro-operations, conditions field $CD$ for four status bits, branch field $BR$ having four options used in conjunction with address field $ADF$. The address space is of $128$ memory locations. The size of micro-instruction is

  1. $17$ bits
  2. $20$ bits
  3. $24$ bits
  4. $32$ bits
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It will be $20$ bits.


There are $3$ fields in the microinstruction.

  1. Micro operation fields.
    $F_{1},F_{2},F_{3}$
  2. $CD$ for status bits
  3. $BR $ in conjunction with $ADF$  i.e we need to multiply possible number of branch field with  Address field.

$F_1$,$F_2$,$F_3$ each are having 7 microoperation .

# of bits to represent it

$\log _{2}7 +\log _{2}7 +\log _{2}7 =3+3+3=9$

$CD$ for status bits$=\log_{2} 4=2$

 

$BR $ in conjunction with $ADF=log_{2}  \,\,(4 \times 128)=9$

 

Total bits=$9+2+9=20$ bits

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Microprocessor instruction format, which is divided into three subfields F1, F2, F3 each having seven distinct micro-operations, condition field CD for four status bits, branch field BR having four options used in conjunction with address field ADF. The address space is of 128 memory locations.ie:
q8
F1,F2,F3 each having seven distinct micro-operation. So, 3 bits are required for each.
Condition field have four status, it needs 2 bits for four different condition.
Branch field have four option so,it needs 2 bits for four option.
Now there are 128 different memory location, So, there 7 bits atre required for 128 diffeent location.
Instruction Field: q8 (1)
Total bits are 20.

Answer:

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