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An N-bit carry lookahead adder, where $N$ is a multiple of $4$, employs ICs $74181$ ($4$ bit ALU) and $74182$ ( $4$ bit carry lookahead generator).

The minimum addition time using the best architecture for this adder is

  1. proportional to $N$

  2. proportional to $\log N$

  3. a constant

  4. None of the above

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5 Answers

Best answer
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48 votes
For $N = 64\ bits$.

Suppose you want to build a $64$ $bit$ adder then you need $16$ $4$-$bit$ ALU and $16$ $4$-$bit$ carry generator, at this point there will be $16$ carries that will ripple through these $16$ ALU modules, to speed up the adder we need to get rid of these $16$ rippling carries, now we can again use $4$ $4$-$bit$ carry generator to generate these $16$ carries, now we have only $4$ carries to ripple through, again we can use the same trick to minimize the rippling of these $4$ carries, we can use an additional $4$-$bit$ carry generator which will generate these carry and we are done :) there will be no more propagation of carry among the ALU modules.

So, we have used $3$ level of $4$-$bit$ carry generator, and the time taken to add $64$ $bits$ will be proportional to $3$ which is $\log _4 64$.

So, in general to add $N$ – bits it takes $\log _4 N$ time.

Correct Answer: $B$
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answer is c

cla contains two stages

1. carry generation stage

2.sum generation stage

it provides constant time for addition

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Answer a)

Parallel processing is not possible here, carry of the current generator depends on the previous one.
Answer:

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