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Consider a 5 stage pipeline that consists of IF, ID, EX, MEM and WB stages.The time taken by these stages are 20ns, 50ns, 60ns, 50ns and 20ns respectively. The pipeline registers are required after every pipeline stage and these pipeline registers consume 10ns, 20ns, 10ns, 20ns and 10ns delay. What is the speedup of the pipeline compared to the corresponding non-pipelined implementation?

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Non Pipelined:

We do not consider pipeline registers delays as there is no pipeline. So,

Time taken by 1 instruction to execute = (20 + 50 + 60 + 50 + 20) = 200 ns 

Pipelined:

Here we will consider pipeline registers delay.

So considering delays, time taken by stages IF, ID, EX, MEM, WB are 30 ns, 70 ns, 70 ns, 70 ns, 30 ns respectively.

In pipelining we consider CPI = 1. 

So time taken by 1 instruction to execute = max( IF, ID, EX, MEM, WB) = 70 ns.


Speed up = Time taken by non pipelined instruction / Time taken by pipelined instruction = 200/70 = 2.857

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