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In RS flip flop, the output of the flip flop at time (t+1) is same as the output at time t, after the occurrence of a clock pulse if 

  1. S=R=1
  2. S=0,R=1
  3. S=1, R=0
  4. S=R=0
in Digital Logic 1.1k views
0
output of the flip flop at time (t+1) is same as the output at time t, after the occurrence of a clock pulse that means previous o/p is reflecting as present o/p.

this is possible when S=R=0.
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i mark this option but dout on first option
0
in S-R flipflop S=R=1  is a invalid combination

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