0 votes 0 votes In $\text{RS}$ flip-flop, the output of the flip-flop at time $(t+1)$ same as the output at time $t$, after the occurrence of a clock pulse if : $S=R=1$ $S=0, R=1$ $S=2, R=0$ $S=R=0$ Digital Logic ugcnetcse-july2018-paper2 digital-logic flip-flop + – Pooja Khatri asked Jul 13, 2018 • edited Feb 12, 2021 by Arjun Pooja Khatri 2.1k views answer comment Share Follow See all 3 Comments See all 3 3 Comments reply Shaik Masthan commented Jul 8, 2018 reply Follow Share output of the flip flop at time (t+1) is same as the output at time t, after the occurrence of a clock pulse that means previous o/p is reflecting as present o/p. this is possible when S=R=0. 0 votes 0 votes pream sagar commented Jul 8, 2018 reply Follow Share i mark this option but dout on first option 0 votes 0 votes Shaik Masthan commented Jul 8, 2018 reply Follow Share in S-R flipflop S=R=1 is a invalid combination 0 votes 0 votes Please log in or register to add a comment.
1 votes 1 votes Option D. S=R=0 R S Qt+1 0 0 No Change 0 1 0 1 0 1 1 1 *race yuviabhi answered Aug 31, 2018 yuviabhi comment Share Follow See all 0 reply Please log in or register to add a comment.
0 votes 0 votes S = R = 0 is the normal resting condition of the flip-flop. It has no effect on the output state of the flip-flop. Both $Q$ and $\bar{Q}$ outputs remain in the logic state they were in prior to this input condition. Mk Utkarsh answered Jul 13, 2018 Mk Utkarsh comment Share Follow See all 0 reply Please log in or register to add a comment.
0 votes 0 votes Option 4 Would Be Correct I.e S=R=0 arnabbarui3 answered Feb 12, 2021 arnabbarui3 comment Share Follow See all 0 reply Please log in or register to add a comment.