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In $\text{RS}$ flip-flop, the output of the flip-flop at time $(t+1)$ same as the output at time $t$, after the occurrence of a clock pulse if :

  1. $S=R=1$
  2. $S=0, R=1$
  3. $S=2, R=0$
  4. $S=R=0$
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Option D. S=R=0

R  S        Qt+1

0   0      No Change 
0  1            0
1  0            1
1  1        *race

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S = R = 0 is the normal resting condition of the flip-flop. It has no effect on the output state of the flip-flop. Both $Q$ and $\bar{Q}$ outputs remain in the logic state they were in prior to this input condition.

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