UGC NET CSE | July 2018 | Part 2 | Question: 94

Question

What does the following logic diagram represent?

• A. Synchronous Counter
• B. Ripple Counter
• C. Combinational Circuit
• D. Mod 2 Counter

Comments

well answer according to me should be b becz its acting like ripple counter first  flip flop clock initiated by external clock and next flip flop clock initiated by the output of first flip flop so thats the property of asynchronous counter or ripple counter.

a is not possible as every flip flop clock are not initiated simultaneously

c is not possible as there is no logic gates and circuit used.

d. in d option when you give J2,K2 both 0 than it acts like mod2 counter but when you give input 1 than it does not act like mod 2

so according to me b is correct..please check..!

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Ripple Counter

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Why not option D

00-10-00

Answer 1

Clearly we can say that Option 1 and Option 2 are not correct.

Printing Mistake, They Don't provide the values for J2 and K2, ===> J2=K2= ?

1) Assume J2=K2=1

 

        then  00 ->01->10->11 where as MSB is Q1 and LSB is Q0 ,  Q0 is initialized to 0 and Q1 is intialized to 0

        then  01 ->10->11->00 where as MSB is Q1 and LSB is Q0 ,  Q0 is initialized to 1 and Q1 is intialized to 0

        then  10 ->11->00->01 where as MSB is Q1 and LSB is Q0 ,  Q0 is initialized to 0 and Q1 is intialized to 1

        then  11 ->00->01->10 where as MSB is Q1 and LSB is Q0 ,  Q0 is initialized to 1 and Q1 is intialized to 1

 

        then  00 ->10->01->11 where as MSB is Q0 and LSB is Q1 ,  Q0 is initialized to 0 and Q1 is intialized to 0

        then  01 ->11->00->10 where as MSB is Q0 and LSB is Q1 ,  Q0 is initialized to 0 and Q1 is intialized to 1

        then  10 ->01->11->00 where as MSB is Q0 and LSB is Q1 ,  Q0 is initialized to 1 and Q1 is intialized to 0

        then  11 ->00->10->01 where as MSB is Q0 and LSB is Q1 ,  Q0 is initialized to 0 and Q1 is intialized to 1

 

        in all these cases it working as Ripple Counter, therefore Option B is Correct

 

2)  Assume J2=K2=0  ===> Q2 o/p is follows the previous one

       

        then  00 ->01 where as MSB is Q1 and LSB is Q0 ,  Q0 is initialized to 0 and Q1 is intialized to 0

        then  01 ->00 where as MSB is Q1 and LSB is Q0 ,  Q0 is initialized to 1 and Q1 is intialized to 0

        then  10 ->11 where as MSB is Q1 and LSB is Q0 ,  Q0 is initialized to 0 and Q1 is intialized to 1

        then  11 ->10 where as MSB is Q1 and LSB is Q0 ,  Q0 is initialized to 1 and Q1 is intialized to 1

 

        then  00 ->10 where as MSB is Q0 and LSB is Q1 ,  Q0 is initialized to 0 and Q1 is intialized to 0

        then  01 ->11 where as MSB is Q0 and LSB is Q1 ,  Q0 is initialized to 0 and Q1 is intialized to 1

        then  10 ->00 where as MSB is Q0 and LSB is Q1 ,  Q0 is initialized to 1 and Q1 is intialized to 0

        then  11 ->01 where as MSB is Q0 and LSB is Q1 ,  Q0 is initialized to 0 and Q1 is intialized to 1

 

        in all these cases it's not working as MOD-2, therefore Option C is not Correct.

 

My Choice is Option B

Answer 2

It is asynchronous counter or ripple counter as output of flipflop drives the clock of another flipflop.

Answer 3

Definitely Ripple counter.

Comments

why not mod 2 counter ?

Because i am getting states as 00 -> 10 ->01->11 .

please correct me if am wrong.

Answer 4

• As one of the main characteristics of Ripple counter is that only one flip-flop is applied with an external clock pulse and another flip-flop clock is obtained from the output of the previous flip-flop.

• The above circuit also uses output of first flip flop drives the clock of another flip flop. Hence, it is ripple counter.