In this Question: A processor that has the carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2′s2′s complement numbers 0100110101001101 and 1110100111101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be
Carry bit is 1 because Carryout is 1
If carry generated by A3+B3 is 1 then auxiliary carry bit is 1 which they dint asked for.
If carry is generated in the middle and not in the MSBs then carry bit is not 1