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Assume that we have three scenarios -

  1.  is a fully associative cache,
  2.  is a two way set associative cache and
  3.  is a direct mapped cache. The cache size is 256 bytes. T

The cache line size is 8 bytes. All variables are 4 bytes.  Assume we have separate instruction and data caches.Assumption -- assign a[1024] to memory locations byte 0 through 4096. Assign b to byte 4096 – 4099, c to byte 4100 to 4103, q to byte 4104-4107, r to byte 4108-4111, i to byte 4112-4115.
Assume data in a cache line is fetched when a cache line is fetched when a cache line is accessed. How many data caches read misses would we see from scenarios and B
A:
1.for(i=0;i<16;i++){
2.b += q*a[i];
3.}
4.for(i=0;i<16;i++){
5.c += r*a[i];
6.}

B:
1.for(i=0;i<16;i++){
2.b += q*a[64*i];
3.}
4.for(i=0;i<16;i++){
5.c += r*a[64*i];
6.}

 

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Assume Memory is Byte Addressable

Here Cache Size =$\text{256 B}$

Cache Block Size =$\text{ 8 B}$

No of blocks in cache=$\frac{256}{8}=32$

Now, $q$ pointing to $\text{4 B}$ starting with $4104$

$q\times a[i]=q\times 4=4\times 4=16B$

Hence, $1$ cache block can contain $16$ such items

So, $1$ block is enough to hold all $16$ items in $A$

-------------------------------------------------------------------------------------------

Now, $256B$ in a cache block

But according to given condition $a[64\times i]$ only $\frac{256}{64\times4}=1$ cache line is used

 So, for $16$ such variable total cache miss will be $16$

Data Cache misses $A$ over $B$ will be $\frac{16\times 16}{1\times 1}=256$

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