Pipeline Stages

Question

The CPU supports the following instructions

LOAD       R₁ , R₂  (100) ; R₂ ← [R₂ + 100]
ADD        R₁ , R₂; R₁ ← R₁ + R₂
SUB        R₂,R₁ ; R₂ ← R₂ – R₁
STORE  R₁ (100), R₂ ; [R₁+100] ←R₂

4 stage pipeline is used to execute the above instructions i.e., Fetch, Decode, Execute and Write Back. Let all instructions consume 1 clock each for fetch, decode and write operations. Execution require 3 clocks for memory related operation and 1 clock is for other instructions. The minimum number of clocks needed with operand forwarding is ________.

Ans. 11.

 

Comments

Please Verify My Answer :-

 

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Yes, your answer is correct. The number of required cycles is indeed 11.

Answer 1

11 cycle are required.

Answer 2

 I think it is 12 clock cycle

Comments

You can do this in 11 clock cycles if we assume operand fetch is done in execution phase 

And 12 clock cycles if we assume operand fetch is done in decoding stage 

Since we want minimum clock cycles we consider the former one correct me if iam wrong 

 

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yeah! normally we take operand in execution phase but not in the case of load and store instructon.the problem with abhishek answer was that assumption of multiple buffer before execution phase. normally single buffer should be taken. i have yet to see gate question to confirm whether we should assume multiple buffer or single buffer