Cache System

Question

In a direct cache controller each main memory address can be viewed as consisting of three fields. The least significant  bits identify a unique word/byte within a block. The cache logic interprets the remaining ‘s’ bits as a tag of (s – r) bits (most significant portion) and a line field of ‘r’ bits. What is the size of main memory and cache memory respectively.

Ans. 2^(s+w) bytes/word and 2^(r+w) bytes/word

Comments

I got that the cache size will be 2^(r+w) but why will the man memory size be 2^(s+w) because tag only represents subset of the memory blocks which are there in cache then how does the above equation justifies ?

---

in this cache memory you did not count the bits stored in cache tag directory..which are part of main memory address bits..so you need to include them to say size of main memory..!

Answer 1

Look brother the main memory has Tag and word offset...now when we do cache mapping we further divide Tag of main memory into Tag and Line offset of cache memory.. and cache memory is not part of main memory it has its own memory area and its addressing is different from main memory..so we do such cache organisation for mapping address of main memory in cache..cache memory is small i.e why it stores some tag bits in tag directory of cache..see the image you will get it..for direct mapping this is the way memory is organised..!

Comments

Please see did i get u right or not,

 If say memory is of K bits and we know that memory is byte addressable so there will be 2^K bytes and we can uniquely identify them. We need tag and offset within memory because when we map words into blocks we have to have there Tag and offset and when its mapped to cache only some part of tag is mapped ?

---

And likewise similar organization of memory is used for set associative ?

---

I get it why do we need cache tag but what's the significance of cache tag directory ?

---

look for mapping some thing in main memory you need all n bits(if main memory of n bits).So,actually what happen is that we use cache in between main memory and CPU...so as to decrease memory access time..so what cache stores it stores pages of main memory na...so it needs to map all n bits which are required to store pages of main memory the bits left after used by cache as Line offset and Word offset,the remaining bits are stored in Tag directory....CPU always generate main memory address ,so mapping should be organized..in such a away

i think you should reach cache topic...you will get more..and its not possible to write everything which i know..its like we can share ideas..so you should read this topic from.some good book..it will help you..!