Doubt regarding SR Flip Flop

Question

Please can anyone explain Clocked S-R FlipFlop with NAND gate Implementation via a Truth Table especially.

Comments

nptel lecture best

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@srestha,Thanks. Actually I was referring Srinivasan Sir's lecture only. But couldn't understand clocked SR Flip-Flop. Then too thank you so much. :)

Answer 1

and the truth table is 

Clock	S	R	Q0n	Q'0n
0	X	X	Q0n	Q'0n
1	0	0	Q0n	Q'0n
1	0	1	0	1
1	1	0	1	0
1	1	1	Q0n	Q'0n

 

for analyzing this, the basics we required about 2-input NAND gate

if atleast one i/p is zero, the NAND gate o/p is 0.

but atleast 1 i/p is one , we can't say any thing, we should depend upon the other i/p

1) when clock is absent ===> clock = 0, then NAND₁ and NAND₂ outputs 1, ===> One of the i/p of NAND₃ and NAND₄ are 1

therefore you have to depend upon previous values in this case

if previously Q₀ =0 and Q'₀ = 1

 i/p of NAND₃ are 1 and 1 ===> output is 0 ===> Q₀=0

 i/p of NAND₄ are 1 and 0 ===> output is 1 ===> Q'₀=1

 

if previously Q₀ =1 and Q'₀ = 0

 i/p of NAND₃ are 1 and 0 ===> output is 1 ===> Q₀=1

 i/p of NAND₄ are 1 and 1 ===> output is 0 ===> Q'₀=0

 

By these points i summarized that when clock=0, output is same as previous values irrespective of S and R values

 

2) CLK=1 , S=0, R=0 ===> NAND₁ and NAND₂ outputs 1, ===> One of the i/p of NAND₃ and NAND₄ are 1

therefore you have to depend upon previous values in this case

if previously Q₀ =0 and Q'₀ = 1

 i/p of NAND₃ are 1 and 1 ===> output is 0 ===> Q₀=0

 i/p of NAND₄ are 1 and 0 ===> output is 1 ===> Q'₀=1

 

if previously Q₀ =1 and Q'₀ = 0

 i/p of NAND₃ are 1 and 0 ===> output is 1 ===> Q₀=1

 i/p of NAND₄ are 1 and 1 ===> output is 0 ===> Q'₀=0

 

By these points i summarized that when clock=1,S=0,R=0, then output is same as previous values .

 

3) CLK=1 , S=0, R=1 ===> NAND₁ outputs 1, and NAND₂ outputs 0, ===> One of the i/p of NAND₃ is 1 but NAND₄ input 0

therefore NAND₄ outputs 1 (Q'₀ = 1), which will be feedback to input of NAND₃ ===> inputs of NAND₃ are 1 and 1 ==> Q₀=0

 

4) CLK=1 , S=1, R=0 ===> NAND₁ outputs 0, and NAND₂ outputs 1, ===> One of the i/p of NAND₃ is 0 but NAND₄ input 1

therefore NAND₃ outputs 1 (Q₀ = 1), which will be feedback to input of NAND₄ ===> inputs of NAND₄ are 1 and 1 ==> Q'₀=0

 

5) CLK=1 , S=1, R=1 ===> NAND₁ outputs 0, and NAND₂ outputs 0, ===> One of the i/p of NAND₃ is 0 and NAND₄ input 0

therefore NAND₃ outputs 1 (Q₀ = 1),  NAND₄ outputs 1 (those outputs are feedbacking but no use ) ==> Q'₀=1 and Q₀=1

due to this reason, we say in S-R flipflop S=R=1 is invalid combination

Comments

@Shaik Masthan,Thank you so much brother.You've lucidly explained the concept. :). A big big big Thanks to you. :)