me tst series dld 1

Question

The total number of NAND gates required to implement a 4 × 1 multiplexer is (assuming a NAND gates of any number of inputs are available) ________.

Comments

Character equation of $4*1 \ MUX \rightarrow I_0\bar x \bar y+I_1\bar xy+I_2x\bar y+I_3xy$
So $7$ NAND gates are required.1 for each product term, 1 for the final sum and 2 NAND gates are required for $\bar x \And \bar y$.

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Is it 2 input nand gate or 3 input nand gate 

If 2 input then 12 Nand gates are required

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@ Soumya29  I THINK U MISSED TWO NAND GATES FOR COMPLEMENTS OF X AND Y ..........TOTAL 7 IS ANSWER GIVEN 

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@eyeamgj, Ohh yes.
Sorry I missed NAND gates for complements.
2 NAND gates are required for $\bar x \And \bar y.$
Updated the comment.

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@Madhur, I am getting 11 if only 2 input NAND gates were allowed.
In the above diagram, you have calculated $\bar S_0$ twice.

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@Soumya29 yes we don't need to do S0(bar) twice  thank u..

Answer 1

For 4:1 mux there will be a sop expression having 4 terms and to implement that 4 term total 7 nand gate required among which 2 nand gate is used to perform complement operation and other 5 nand gate is used at level 1 and level 2.