First level data cache: Direct mapping , writeThrough/write allocate , 8kb data and lines of 8 bytes, miss rate= 17%
First level instructions cache: Direct mapping,, 4kb data and lines of 8 bytes, miss rate= 2%
Second level unified cache: 2-way associative, write-back/write-allocate, 2 mb data and lines of 32 bytes, miss rate= 12%, 50% of the lines has true dirty bit
Hit time l1= 1c , Hit time l2= 10c, access time to main memory= 100 c for the first word of the bus width and then each word of the bus takes one cycle. There is a 128-bit wide bus between the second cache level and main memory and 64 bits wide between l1 and l2
1) What percentage of data memory accesses cause one access to main memory?
2) How many bits are needed to index each of the caches?
3) In what case is memory access given slower? How many cycles does it demand?
4) Assuming that 30% are data memory accesses, what is the percentage of accesses to data memory and instructions of the total number of accesses?
5)What is the average memory access time?