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The instruction format of a CPU is:

\begin{array}{|c|c|c|} \hline  \text {OP CODE} &  \text{MODE}& \text{RegR} \\\hline \end{array}\begin{array}{|c||}   \text {___one memory word___}  \end{array}


$\text{Mode}$ and $\text{RegR}$ together specify the operand. $\text{RegR}$ specifies a CPU register and $\text{Mode}$ specifies an addressing mode. In particular, $\text{Mode}=2$ specifies that ‘the register $\text{RegR}$ contains the address of the operand, after fetching the operand, the contents of $\text{RegR}$ are incremented by $1$'.

An instruction at memory location $2000$ specifies $\text{Mode}= 2$ and the $\text{RegR}$ refers to program counter (PC).

  1. What is the address of the operand?

  2. Assuming that is a non-jump instruction, what are the contents of PC after the execution of this instruction?

in CO and Architecture by Veteran (52.2k points)
edited by | 2.1k views

2 Answers

+23 votes
Best answer
  1. Address of the operand $=$ content of PC $= 2001$ as PC holds the address of the next instruction to be executed and instruction size is $1-word$ as given in the diagram.
  2. After execution of the current instruction PC will be automatically incremented by $1$ when the next instruction is fetched. Also on extra increment will be done by operand fetch. So, PC $= 2003$ supposing next instruction is fetched. If we assume next instruction fetch is not done (this should be the default here), it should be $2002$.
by Veteran (431k points)
edited by
PC is concerned with address of next instruction.What is extra increment for ?Plz explain @Arjun Sir

As per the question, PC will also be incremented after operand fetch . So, here PC will be incremented twice. Once for automatic increment of PC after instruction fetch and another after operand fetch. That is why increment happens twice.

our current instruction is at memory location 2000 and pc = 2000

1. fetch the instruction and increment the pc with step size ie 1 now pc =2001

2.Decode the instruction

3.operand fetch that is content of pc ie 2001 so address of operand is 2001

4. now in execution step now increment the regR ie PC now pc =pc + 1=2002

so for 2nd question ans should be 2002 arjun sir plzz tell me where m i wrong. If.
very well explained broooo
@saurabh rai

when it will go to execution till that time 1 more instruction will arrive in fetch cycle. so if that instruction would have arrived,   then it would be 2003(means fetch is done ) otherwise only REGR will get incremented by 1, so it will be 2002.
If an instruction is stored in X location and it's MODE=2 then, Operand address is X+1. So. next instruction is stored at X+2 location, that is why one extra increment is required (when MODE=2 ).

MODE=2 then,   X --->current instruction's location, X+1 -----> it's Operand Address , X+2---> Next instruction's address
very well explain @Arjun sir
"Reg R refers to Program counter" means Reg R is nothing but PC.

isnot Reg R is instruction register?
I think here in instruction, RegR is address of PC register.(Question also says, RegR refers to PC).
Can anyone explain " one extra increment will be done by operand fetch"??
@Ayush Upadhyaya

Did you understand why PC value should be 2003 at the end?

I think it should be 2002.

Bcoz since current instruction is at 2000, once it's fetch is done, its PC gets incremented and points to 2001, which is the operand, so after fetch of operand the content of PC becomes 2002. Why we r again incrementing PC after execution of instruction at 2000.

As far as I know, after fetch of an instruction, PC gets incremented and points to next instruction, then why to increment after execute too?



it is 2003, if the next instruction is fetched

but in the question it is not specified so, we doesn't fetch next instruction ===> 2002 is the correct answer

+4 votes
We will

      1) Fetch the instruction at 2000 and increment PC to point to next instruction which will be at 2001 .. So 2001 ... Here RegR will be having 2001 and after operand fetching we will make RegR as 2002
by Loyal (8k points)
thanks @vicky ....very good explanation

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