in CO and Architecture
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Please Explain Every Point :)

Ans. All are Correct

in CO and Architecture

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S1: Burst Mode DMA technique is used to transfer Bulk size of Data transfer.

An entire block of data is transferred in one contiguous sequence. Once the DMA controller is granted access to the system bus by the CPU, it transfers all bytes of data in the data block before releasing control of the system buses back to the CPU, but renders the CPU inactive for relatively long periods of time. The mode is also called "Block Transfer Mode".

S2: Hold (bus request) has highest priority than all interrupt request signals.

HOLD (Hold) is a control signal input and HLDA (Hold acknowledge) is a control signal output. These two signals are used for handshaked control during DMA operation (Direct Memory Access). These two signals are used where there is more than one CPU like devices sharing the same system bus. The device asking for DMA makes the HOLD signal input HIGH. The processor which continuously monitors the HOLD signal input during each machine cycle recognizes that an external device is requesting for a DMA. 

DMA REQ $\equiv$ HOLD 

DMA ACK $\equiv$ HLDA

I've not read anywhere that Hold has the highest priority then all interrupt request signals. There can be more interrupts in different microprocessors with different priorities.

S3: Device supplies its address to the processor after receiving the signal from vectored hardware interrupt.

There can be n number of I/O devices. A vector is an identification for each I/O device connected to the processing unit. This identification vector can be also called as address. If a vector hardware interrupt does not send the identification to the processing unit then CPU cannot load device interrupt service routine. These are interrupt routines which are different for different I/O devices. 

S4: Interrupt driven I/O is used for connecting the devices like printer.

Printer can also work on programmed I/O.

S5: In programmed I/O type data transfer technique, the processor is idle for long time to get rediness signal from the device.

The processor is idle because it is programmed to poll I/O devices in some sequence depending upon the priority or any other reason. Hence an I/O device has to wait till the processor initiates the I/O interrupt.

S6: In interrupt driven I/O, only one word is transferred for one interrupt request.

  •  The processor issues a READ command.

  •  It then does something else(e.g. the processor may be working on several different programs at the same time)

  •  At the end of each instruction cycle, the processor checks for interrupts

  • When the interrupt from an I/O module occurs, the processor saves the context (e.g. program counter & processor registers) of the current program and processes the interrupt.

  •  In this case, the processor reads the word of data from the I/O module and stores it in memory.

  • If then restores the context of the program it was working on and resumes execution.

This word is an address or a specific identifier for I/O device.

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