59 views reshown | 59 views
0
No. of stages is not given then what to assume? 5? If yes then max speed up possible is 5. How can it exceed that when there are stalls in the pipeline? :/
0

I am not able to understand this solution can you plz explain if yes 0
Why are they doing 5*0.5 and 5*0.3!! :O

Sorry even I also can't understand :(

Which test series?
0
I think there is something wrong with the options and the provided solution.

Non-pipeline=(4*0.4+5*0.2+6*0.4)*10=50ns

Speedup=non-pipeline/pipeline=50/12=4.167
0

Bhagyashree Mukherje

Is it correct to assume that this pipeline takes 1 clock cycle per instruction even when there is non uniformity in the pipeline? Like the no. of cycles required by different types of instructions is different, branch and memory types require more cycles so they should be introducing stalls in the pipeline, so the Tavg should be more than 1 i think.

0
Since nothing is mentioned explicitly, in such type of questions we generally take 1 clock pr cycle.In one clock cycle, 1 instruction gets executed