The Gateway to Computer Science Excellence
0 votes
59 views

in CO and Architecture by (25 points)
reshown by | 59 views
0
No. of stages is not given then what to assume? 5? If yes then max speed up possible is 5. How can it exceed that when there are stalls in the pipeline? :/
0

I am not able to understand this solution can you plz explain if yes

0
Why are they doing 5*0.5 and 5*0.3!! :O

Sorry even I also can't understand :(

Which test series?
0
I think there is something wrong with the options and the provided solution.

Non-pipeline=(4*0.4+5*0.2+6*0.4)*10=50ns

Pipeline =10ns+overhead=12ns

Speedup=non-pipeline/pipeline=50/12=4.167
0

Bhagyashree Mukherje

Is it correct to assume that this pipeline takes 1 clock cycle per instruction even when there is non uniformity in the pipeline? Like the no. of cycles required by different types of instructions is different, branch and memory types require more cycles so they should be introducing stalls in the pipeline, so the Tavg should be more than 1 i think.

0
Since nothing is mentioned explicitly, in such type of questions we generally take 1 clock pr cycle.In one clock cycle, 1 instruction gets executed

Please log in or register to answer this question.

Related questions

Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true
50,666 questions
56,154 answers
193,759 comments
93,729 users