0 votes 0 votes BHASHKAR asked Aug 15, 2018 reshown Aug 15, 2018 by BHASHKAR BHASHKAR 344 views answer comment Share Follow See all 6 Comments See all 6 6 Comments reply MiNiPanda commented Aug 15, 2018 reply Follow Share No. of stages is not given then what to assume? 5? If yes then max speed up possible is 5. How can it exceed that when there are stalls in the pipeline? :/ 0 votes 0 votes BHASHKAR commented Aug 15, 2018 reply Follow Share I am not able to understand this solution can you plz explain if yes 0 votes 0 votes MiNiPanda commented Aug 15, 2018 reply Follow Share Why are they doing 5*0.5 and 5*0.3!! :O Sorry even I also can't understand :( Which test series? 0 votes 0 votes Bhagyashree Mukherje commented Aug 16, 2018 reply Follow Share I think there is something wrong with the options and the provided solution. Non-pipeline=(4*0.4+5*0.2+6*0.4)*10=50ns Pipeline =10ns+overhead=12ns Speedup=non-pipeline/pipeline=50/12=4.167 0 votes 0 votes MiNiPanda commented Aug 16, 2018 reply Follow Share Bhagyashree Mukherje Is it correct to assume that this pipeline takes 1 clock cycle per instruction even when there is non uniformity in the pipeline? Like the no. of cycles required by different types of instructions is different, branch and memory types require more cycles so they should be introducing stalls in the pipeline, so the Tavg should be more than 1 i think. 0 votes 0 votes Bhagyashree Mukherje commented Aug 16, 2018 reply Follow Share Since nothing is mentioned explicitly, in such type of questions we generally take 1 clock pr cycle.In one clock cycle, 1 instruction gets executed 0 votes 0 votes Please log in or register to add a comment.