0 votes 0 votes Encode the instruction sub r1, r2, 3 (a) 00001 0 0001 0010 00 0000 0000 0000 0011 (b)00001 1 0001 0010 00 0000 0000 0000 0011 (c) 00011 1 0001 0010 00 0000 0000 0000 0111 (d)None of the above BASANT KUMAR asked Aug 16, 2018 BASANT KUMAR 433 views answer comment Share Follow See all 4 Comments See all 4 4 Comments reply Shaik Masthan commented Aug 17, 2018 reply Follow Share with out knowing the SUB instruction implement ( how many instructions are there in your Instruction Set Architecture and etc..), and how many registers you have.. we can't answer this type of questions 1 votes 1 votes goxul commented Aug 17, 2018 reply Follow Share As @Shaik pointed it out, this is specific to the Instruction Set Architecture of the processor. Without knowing the opcodes for SUB and the memory location of R1 and R2, it is not possible. 0 votes 0 votes BASANT KUMAR commented Aug 17, 2018 reply Follow Share in question only above information is given. 0 votes 0 votes goxul commented Aug 17, 2018 reply Follow Share If that's the case, the question is incorrect. 0 votes 0 votes Please log in or register to add a comment.
