A 32-bit adder can be designed using 8 cascaded 4-bit CLA Adders.
Since each adder will ripple it's carry to the next, there is a need to ripple the carry 7 times (between every pair of adjacent CLAs) and to generate a carry in a CLA it take 3 gate delays hence we have 3x7= 21 gate delays.
Now the last one has carry-in signal which it can use to generate the sum bits which would take another 3 gate delays hence 21 + 3 = 24 gate delays.