365 views

1 Answer

1 votes
1 votes
A 32-bit adder can be designed using 8 cascaded 4-bit CLA Adders.

Since each adder will ripple it's carry to the next, there is a need to ripple the carry 7 times (between every pair of adjacent CLAs) and to generate a carry in a CLA it take 3 gate delays hence we have 3x7= 21 gate delays.
Now the last one has carry-in signal which it can use to generate the sum bits which would take another 3 gate delays hence 21 + 3 = 24 gate delays.

Related questions

0 votes
0 votes
1 answer
1
val_pro20 asked May 16, 2019
1,059 views
$Exclusive-OR$ gate has a propagation delay of $10$ ns and that the $AND$ or $OR$ gates have a propagation delay of $5$ ns.What is the total propagation delay time in the...
2 votes
2 votes
1 answer
4
sh!va asked Jul 16, 2016
669 views
Which of the following statements is/are true?S1: Carry look ahead adder is faster compared to a ripple carry adder.S2: The cost is higher for a carry look ahead adder co...