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A full adder circuit takes 20 ns to generate the carry-out bit and 40 ns for the sum bit. When 4, 1 bit full adders are cascaded, the maximum rate of additions per second will be $\text{____} \times 10^6 $sec.

Usual Solution given

The answer usually given is 100ns to generate addition of all 4 bits:

(3*20ns) + 40ns = 100ns

3 since 20 ns delay of generating carries is rippled / forwarded thrice. 40ns is required to generate sum at first FA.

So in 1 s, there will be 1/100ns = 10 * 10^6 additions per seconds.


Consider numbers given to gates in the below diagram:

How it is correct to keep adding delay of calculating carry to delay of calculating sum?

When FAs are cascaded, FA1-C is added to FA2-XOR2 to generate FA2-S (Red 1 in the diagram).

It is also followed by FA2-AND2 and FA2-OR to generate FA2-C (Red 2 and 3 in the diagram)

Next FA2-C is added to FA3-XOR2 to generate FA3-S

It its also followed by FA3-AND2 and FA3-OR to generate FA3-C

And so on.

So in generating FA1-C we have to consider delay of AND1.

But in in generating subsequent Cs, we dont consider AND1 delays.

In fact, all HA1-S and HA1-Cs are available after fixed time as they do not depend on inputs from earlier FAs at LSBs.

That means we cannot simply keep adding delays of carry generation to time taken to calculate sum at lesser significant bit to calculate time taken to generate sum at current bit. Right?

I guess, here we have not given delay of AND2,OR and XOR2. So we cannot really calculate the total time taken to perform one round of four bit addition. Right?

(Similar old question:

in Digital Logic by Active (2.5k points)
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1 Answer

+1 vote
In such questions you're not supposed to dissect the full adders or half adders. Those are IC chips working as a whole. And the AND gates used outside of the FAs are having negligible delays.
by Active (3.3k points)

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