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A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2$ nanoseconds, $20$ nanoseconds and $200$ nanoseconds for $L1$ cache, $L2$ cache and the main memory unit respectively.

When there is a miss in $L1$ cache and a hit in $L2$ cache, a block is transferred from $L2$ cache to $L1$ cache. What is the time taken for this transfer?

1. $2$ nanoseconds
2. $20$ nanoseconds
3. $22$ nanoseconds
4. $88$ nanoseconds

How high are the people setting these questions? Vaguest question award goes to this one!
I read this question 4 to 5 times and spent an hour on this. :(

Ideally the answer should be $20$ ns as it is the time to transfer a block from $L2$ to $L1$ and this time only is asked in question. But there is confusion regarding access time of $L2$ as this means the time to read data from $L2$ till CPU but here we need the time till $L1$ only. So, I assume the following is what is meant by the question.

A block is transferred from $L2$ to $L1$. And $L1$ block size being $4$ words (since $L1$ is requesting we need to consider $L1$ block size and not $L2$ block size) and data width being $4$ bytes, it requires one $L2$ access (for read) and one $L1$ access (for store). So, time $= 20+2 = 22$ ns.

Correct Answer: $C$
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When we talk about Cache to Memory, we use term "lines" and Cache and memory has same block size. Just like that when we talk about Memory to Disk, we use term "pages" and page size is same for Memory and Disk. In this question, L1 has 4 words block size which we can say it is for both L1 and L2. And L2 has 16words block size which we can say it is for both L2 and Memory. So only 4 words will be transferred from L2 not 16 words. Hence Answer is (20+2)=22ns.

And for second part of this whole question answer is (200+20)*4+(20+2)=902ns.
Yes then answer could be 88. Made Easy PYQ book has given ans as 88. As data bus is of 4 word nd we're sending 4 blocks, still answer would have been 80.

This question deserves to be left aside, is of absolutely no use at all..

Did BARC 2017 provide key to this?
In case of miss at lower level cache, it is not possible to transfer specific 4 words from higher level cache block to lower level cache block. So we must transfer the whole 16 word block and it requires 4 access at both the ends. Leaving us with answer 88 ns.

The size to transfer a block is always decided by source(Do not confuse yourself by looking "a block is transferred from L2 cache to L1 cache). In this case only 4 words will be transferred from L2 to L1 not whole block of L2. Now the only confusion is "This whole process of transferring block is concurrent process or serial?".

If nothing is mentioned in the question then take serial transfer of block(in computer science we always strive for Worst case) so 20ns to access or read L2 cache and 2ns to place or write it into L1 cache. so answer would be 22ns.

what happens for parallel transfer?

@Nitesh Singh 2

it seems that you have assumed parallel transfer, because in case of serial it will be 24 ns .

This question statement and diagram depicts that it is based on parallel hierarchy means direct access to L1,L2 or main memory is possible in it.

Since L1 miss

20 ns is required to access L2 and reading a block of size 16B.Since L1 is requesting which has block size of 4 B .only 4B transfer to L1 from L2 is required which takes an access of L1 to store block in it.

Thus L2 access (reading a block) + L1 (storing a block since it is parallel hierarchy by default it will not be copied to L1)

thus 20ns + 2ns = 22ns

Ans C

(storing a block since it is parallel hierarchy by default it will not be copied to L1)

How do we know the given memory organisation is parallel or hierarchical?
Any per my knowledge. Any read/write operation occurs in this sequence

1. Read the data from the source.

2. Write the data to the destination.

Now 2 ns is the time to access the L1 cache. And 20 ns to access the L2 cache. The data bus is 4 words wide. Also any block transfers as a whole.

So consider the following sequence.

1. Read from L2 -->20 ns.

2. Write to L1 -->2 ns. (4 words written).

3. Read from L2 -->20 ns.

4. Write to L1 -->2 ns. (4 words wasted).

5. Read from L2 -->20 ns.

6. Write to L1 -->2 ns. (4 words wasted).

7. Read from L2 -->20 ns.

8. Write to L1 -->2 ns. (4 words wasted).

So in total 20+2+20+2+20+2+20+2=88 ns.

Therefore it must take 88 ns to transfer a block from L2 to L1 cache.
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