The correct answer is 88ns.
When there is a miss in L1 then entire block is going to move from L2 to L1. Block Size of L2 is 16 Words but system bus is capable of 4 words at a time. Hence, 4 times transfer operation will perform. here will also add the latency of L1 along with transfer time i.e.
1. (20+2)=22
2. (20+2)=22
3. (20+2)=22
4. (20+2)=22
Total = 88ns.
Here the only trick is, although we know that the entire block is transferred from L2 to L1 of size 16 words. But system bus limited to 4 words at a time. Thats a confusion part of the question but has been defined clearly in the diagram. Diagram need to be considered seriously.
If the diagram is not given, or its not been mentioned that the system bus is limited to 4 words at a time, then the answer could be 22ns.
yes, in ideal case the answer could also be 20ns where stalls/instructions are negligible i.e stalls created when miss occurs is neglected. But question does not say anything ideal, hence we should go with counting L1 latency too.